Xuanyao Fong

KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

The storage device in spin-transfer torque MRAM (STT-MRAM) is the magnetic tunneling junction (MTJ) and several models for the MTJ have been proposed. However, a simulation framework that captures device physics at the atomistic level when simulating STT-MRAM at the bit-cell level is lacking. We propose a simulation framework (KNACK) which models the MTJ at the atomistic level using the Non-Equilibrium Greens Function (NEGF) formalism and uses the NEGF model in conjunction with our STT-MRAM bit-cell circuit model for circuit-level simulations. Our simulation framework accepts I–V and C-V characteristics of the access device input either as lookup tables or as compact models. We show that with appropriate device and bit-cell parameters, our simulation framework has the ability to capture MTJ physics and simulate different genres of STT-MRAM bit-cells with results in agreement with experiments.

Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching

Spin-transfer torque magnetic random access memories (STT-MRAM), using magnetic tunnel junctions (MTJ), is a resistive memory technology that has spurred significant research interest due to its potential for on-chip, high-density, high-speed, low-power, and non-volatile memory. However, due to conflicting read and write requirements, there is a need to develop optimization techniques for designing STT-MRAM bit-cells to minimize read and write failures. We propose an optimization technique that minimizes read and write failures by proper selection of bit-cell configuration and by proper access transistor sizing. A mixed-mode simulation framework was developed to evaluate the effectiveness of our optimization technique. Our simulation framework captures the transport physics in the MTJ using Non-Equilibrium Greens Function method and self-consistently solves the MTJ magnetization dynamics using Landau-Lifshitz-Gilbert equation augmented with the full Slonczewski spin-torque term. The electrical parameters of the MTJ are then encapsulated in a Verilog-A model and used in HSPICE to perform bit-cell level optimization. The optimization technique is applied to STT-MRAM bit-cells designed using 45 nm bulk and 45 nm silicon-on-insulator CMOS technologies. Finally, predictions are made for optimized STT-MRAM bit-cells designed in 16 nm predictive technology.

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

The emergence of spin-transfer torque magnetic RAM (STT-MRAM) as a leading candidate for future high-performance nonvolatile memory has led to increased research interest. Current STT-MRAM technology faces several major obstacles in attaining its potential. One of the major issues is in the design of 1T-1MTJ STT-MRAM bit-cells under process variations: the bit-cells need to be significantly upsized to improve bit-cell failure, resulting in increased bit-cell area and power dissipation. In this paper, we analyze four circuit-level solutions that enable smaller 1T-1MTJ STT-MRAM bit-cells with improved yield, namely, bit-line voltage boosting, word-line voltage boosting, access transistor body biasing, and an applied external magnetic field. Results from simulation using 45-nm bulk CMOS access transistor and 40-nm magnetic tunneling junction technology show that word-line voltage boosting can be the best failure mitigation technique. Bit-cells designed with word-line boosting for write has a bit-cell area reduced by > 75% at iso-failure probability, compared to bit-cells without any failure mitigation technique. When bit-cell failure probability is optimized instead, 5 Oe of applied external magnetic field assisted write reduces power consumption by 15% , compared to bit-cells designed without failure mitigation techniques.

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic.

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a state-of-the-art spin-transfer-torque based magnetic random access memories (STT-MRAM) bit-cell in the presence of parametric process variations. In order to realize ultra low power under process variations, we propose device, bit-cell and architecture level design techniques. Such design methods at various levels of design abstraction has been found to achieve substantially enhanced robustness, density, reliability and low power as compared to their charge-based counterparts for future embedded applications.

Spin-orbit torque induced spike-timing dependent plasticity

Nanoelectronic devices that mimic the functionality of synapses are a crucial requirement for performing cortical simulations of the brain. In this work, we propose a ferromagnet-heavy metal heterostructure that employs spin-orbit torque to implement spike-timing dependent plasticity. The proposed device offers the advantage of decoupled spike transmission and programming current paths, thereby leading to reliable operation during online learning. Possible arrangement of such devices in a crosspoint architecture can pave the way for ultra-dense neural networks. Simulation studies indicate that the device has the potential of achieving pico-Joule level energy consumption (maximum 2 pJ per synaptic event) which is comparable to the energy consumption for synaptic events in biological synapses.

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM

In recent years, Physical Unclonable Function (PUF) based on the inimitable and unpredictable disorder of physical devices has emerged to address security issues related to cryptographic key generation. In this paper, a novel memory-based PUF based on Spin-Transfer Torque (STT) Magnetic RAM, named as STT-PUF, is proposed as a key generation primitive for embedded computing systems. By comparing the resistances of STT-MRAM memory cells which are initialized to the same state, response bits can be generated by exploiting the inherent random mismatches between them. To enhance the robustness of response bits regeneration, an Automatic Write-Back (AWB) technique is proposed without compromising the resilience of STT-PUF against possible attacks. Simulations show that the proposed STT-PUF is able to produce raw response bits with uniqueness of 50.1% and entropy of 0.985 bit per cell. The worst-case Bit-Error Rate (BER) under varying operating conditions is 6.6 × 10-6.

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owing to the high spin injection efficiency of SHE, the estimated write current for backup operation is lower than 40 μA. Due to the low write current requirement, we do not introduce a dedicated write driver circuit. Instead, we utilize the cross-coupled inverters in the slave latch to perform the backup operation, resulting in low area overhead. The simulation results show 10× improvement in backup energy when compared with previous works on spin transfer torque-based NVFFs.

A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems

CMOS device scaling is facing a daunting challenge with increased parameter variations and exponentially higher leakage current every new technology generation. Thus, researchers have started looking at alternative technologies. Magnetic Quantum Cellular Automata (MQCA) is such an alternative with switching energy close to thermal limits and scalability down to 5nm. In this paper, we present a circuit/architecture design methodology using MQCA. Novel clocking techniques and strategies are developed to improve computation robustness of MQCA systems. We also developed an integrated device/circuit/system compatible simulation framework to evaluate the functionality and the architecture of an MQCA based system and conducted a feasibility/comparison study to determine the effectiveness of MQCAs in digital electronics. Simulation results of an 8-bit MQCA-based Discrete Cosine Transform (DCT) with novel clocking and architecture show up to 290X and 46X improvement (at iso-delay and optimistic assumption) over 45nm CMOS in energy consumption and area, respectively.

Multilevel Spin-Orbit Torque MRAMs

In this paper, we present two multilevel spin-orbit torque magnetic random access memories (SOT-MRAMs). A single-level SOT-MRAM employs a three-terminal SOT device as a storage element with enhanced endurance, close-to-zero read disturbance, and low write energy. However, the three-terminal device requires the use of two access transistors per cell. To improve the integration density, we propose two multilevel cells (MLCs): 1) series SOT MLC and 2) parallel SOT MLC, both of which store two bits per memory cell. A detailed analysis of the bit-cell suggests that the S-MLC is promising for applications requiring both high density and low write-error rate, and P-MLC is particularly suitable for high-density and low-write-energy applications. We also performed iso-bit-cell area comparison of our MLC designs with previously proposed MLCs that are based on spin-transfer torque MRAM and show 3-16× improvement in write energy.