Charles E. Dike

Miller and noise effects in a synchronizing flip-flop

The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on T/sub m/ and /spl tau/. The flip-flop was fabricated on a 0.25-/spl mu/m CMOS process.

An asynchronous instruction length decoder

This paper describes an investigation of potential advantages and pitfalls of applying an asynchronous design methodology to an advanced microprocessor architecture. A prototype complex instruction set length decoding and steering unit was implemented using self-timed circuits. [The Revolving Asynchronous Pentium/sup (R)/ Processor Instruction Decoder (RAPPID) design implemented the complete Pentium II/sup (R)/ 32-bit MMX instruction set.] The prototype chip was fabricated on a 0.25 /spl mu/m CMOS process and tested successfully. Results show significant advantages - in particular, performance of 2.5-4.5 instructions per nanosecond - with manageable risks using this design technology. The prototype achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as the fastest commercial 400 MHz clocked circuit fabricated on the same process.

A 900 Mb/s bidirectional signaling scheme

Traditional approaches to the interchip communication problem have consisted of unidirectional signal flow on either a point-to-point interconnect or a shared bus. For systems in which the electrical length of the interconnect is significant in relation to the edge rate or fundamental frequency of the signals traversing them and operation at the highest possible speeds is desired, the interconnect medium consists of controlled impedance traces terminated in their characteristic impedance. The goal of these interconnect designs is to obtain the optimum combination of bandwidth, number of wires, power, and cost. The traditional schemes require a wire for each component output along with the required termination resistors in order to achieve the highest possible bandwidth. The bidirectional method described here allows data transmission simultaneously in two directions over one wire. This doubles the effective bandwidth per pin over a point-to-point unidirectional scheme operating at the same frequency. The line termination is provided by the driver, eliminating discrete terminations from the board. When the drivers at both ends of the line are in the same state, no power is consumed in the I/Os. This can result in significant power savings. Bidirectional schemes have been proposed previously but required current mode signaling and explicit terminations.

A design for digital, dynamic clock deskew

Unintentional clock skews between clock domains represent an increasing and costly overhead in high-performance VLSI chips. We describe a novel yet easy-to-implement design that reduces skew between local clock domains dynamically or statically by sensing clock-delay differences and then tuning the clock of each domain relative to its neighbors. Lowering local clock skew is accomplished without compromising worst-case global skew.

On-Chip Measurement of Deep Metastability in Synchronizers

A deep metastability measurement scheme has been implemented on chip using digital circuits with 0.18 mum technology. Compared with previous off-chip implementations using analog circuits, the on-chip implementation allows integration of both the synchronizer circuits and the measurement method, and eliminates high-speed off-chip paths which are a source of inaccuracy. It also makes control at the picosecond level easier because of the inherent stability of digital integrating counters and digital delay lines. Our results show that the digital delay line used to adjust the data to clock times is controllable to an increment of 0.1 ps, and the input time distribution is 5.2 ps compared with 7.6 ps for the analog version. Because of the use of high and low counters, we can control the ratio of high to low outputs so that the actual input distribution can be measured to within better than 1 ps. The metastability time constant tau has been measured down to 10-17 s which corresponds to an mean time between failures (MTBF) of 100 seconds in an experimental time of 10 minutes and can be extended to a lower level by increasing the measurement time. Our results also show that a new synchronizer circuit designed for robustness to variation in Vdd performed at least as well as the Jamb Latch at all values of Vdd, and is more than 20% faster when Vdd was reduced by 25%.

A fast resolving BiNMOS synchronizer for parallel processor interconnect

The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer. >

Measuring Deep Metastability and Its Effect on Synchronizer Performance

Present measurement techniques do not allow synchronizer reliability to be measured in the region of most interest, that is, beyond the first half cycle of the synchronizer clock. We describe methods of extending the measurement range, in which the number of metastable events generated is increased by four orders of magnitude and events with long metastable times are selected from the large number of more normal events. The relationship found between input times and the resulting output times is dependent on accurate measurement of input time distributions with deviations of less than 10 ps. We show how the distribution of to clock times at the input can be characterized in the presence of noise and how predictions of failure rates for long synchronizer times can be made. Anomalies such as the increased failure rates in a master-slave synchronizer produced by the back edge of the clock are explained and demonstrated.

FA 18.4: a phase-tolerant 3.8 GB/s data-communication router for a multiprocessor supercomputer backplane

Recent parallel processor supercomputer designs use an active backplane of routers to form the interconnections between processing elements. Today, high-bandwidth interconnect systems capable of scaling to configurations with more than 500 processing nodes tend to use self-timed designs. This avoids clock distribution problems seen in large phase-sensitive synchronous systems. The BiCMOS routing component described in this paper employs 200 MHz clocked communication for large scalable parallel-processor supercomputer systems. This scheme eliminates need for clock edges to be phase-aligned across the clock distribution network. Additionally, router inputs accept data at any phase relationship to the receiving router internal clock.<<ETX>>