Jerry Jex

Flash memory BIOS for PC and notebook computers

The author describes a flash memory device used to store the basic input/output system (BIOS) of a PC or notebook computer. Rapidly increasing computer complexity requires rapid and convenient BIOS modifications. BIOS code can be stored in ROM, EPROM, EEPROM, bulk erasable flash memory, or block erasable flash memory. Updating BIOS stored in ROM or EPROM requires much time and money. BIOS storage does not require EEPROMs feature of byte erasure. Rapid and inexpensive BIOS revisions can be accomplished in flash memory with update software provided on a desk or by modem. Block erasable flash memory provides the capability of BIOS updates while providing boot and recovery code protected from inadvertent program or erasure. BIOS code is easily updated in flash memory containing an internal program and erase sequence controller. A 1-Mb block erasable flash memory with an internal program and erase sequence controller is an ideal storage medium for PC and notebook computer BIOS code.<<ETX>>

A fast resolving BiNMOS synchronizer for parallel processor interconnect

The design, testing, and application of a BiNMOS metastability resolving synchronizer is described. High speed signaling requires multiple clock cycle metastability settling time. The integrated circuit provides low tau (fast resolution) and is considered one of the fastest synchronizers available to date. The circuit reduces metastability failure with a high gain-bandwidth product and longer settling time per clock cycle. High gain-bandwidth product is accomplished with n-p-n transistors driving a cross-coupled inverter latch with reduced node capacitance. Longer settling time is provided by omitting metastability immune circuitry and using a parallel staged synchronizer. >

Content addressable memory for flash redundancy

The authors describe content addressable memory (CAM) used on a 1-Mb flash memory. Yield is improved by replacing defective columns containing fatal random defects. The CAM provides the address of a redundant column as an output needed to implement column redundancy. Novel placement of the CAM can decrease redundant CAM area, decreases the total chip area, and increases the redundancy efficiency.<<ETX>>

Split FIFO phase synchronization for high speed interconnect

This paper describes a simple method of phase synchronization for high speed communication in a large distributed network such as a parallel processor interconnect. Reducing phase delta with matched clock distribution in a distributed system is not always practical. A split FIFO phase synchronizer provides reliable data transfer at fast clock speeds and high bandwidth. A digital delay locked loop, DLL, centers the data clock midway in the data bit cell. A reset arbiter/synchronizer provides proper alignment of the read and write pointer release during initialization of the split FIFO synchronizer.

High speed I/O circuit design in multiple voltage domains

Designing I/O drivers and receivers that must work across multiple voltage domains has several unique circuit-design challenges. One challenge is limitations due to process silicon breakdown voltage. A second disadvantage is the need to transition voltage levels. This is typically done with differential amplifier receivers, special high voltage N or P devices, external pull-ups, or voltage translators. Due to differences in switching levels, matching T/sub CO/ delays though identical receivers in different voltage domains will require additional consideration. Finally, system level simulations of chips crossing multiple voltage domains require 4 terminal devices, non-single global power supply nodes, and must handle multiple process technology files.