Charles E. Radke

The use of quadratic residue research

Some of the problems of simulating discrete event systems, particularly computer systems, on a conventional digital computer are dealt with. The systems are assumed to be described as a network of interconnected sequential processes. Briefly reviewed are the common techniques used to handle such simulations when simultaneous events do not occur, can be ignored, or can be handled by simple priority rules. Following this, the problem of dealing with simultaneous events in separate processes is introduced. An abstraction of this problem is developed which admits solution for a majority of commonly encountered problems. The technique will either find a method of simulating the parallel events or report that none can be found. In some of the latter cases it is shown to be possible to find a solution by extending the information available to the solution technique, but in many cases the technique becomes computationally unfeasible when the additional information is provided.

Quality Level and Fault Coverage for Multichip Modules

A relationship between the quality level of a multichip module package and test coverage is established. A fault model for each stage of assembly of the package is assumed and the contribution of each of these stages to the quality level is assessed to produce the required relationship to test coverage achieved through test generation programs.

A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratios

A rule for describing the circuit-to-pin relation has been quite useful as an aid to the packaging of electronic components in data processing machines. This rule, which in some circles is referred to as the Rents Rule, is expressed as XN &equil; aXBr where XB is the number of circuits and XN is the number of pins per package. Historically Rents Rule was established from experimental data which produced a close to linear pin-to-circuit relation on a log-log plot. In the past, the parameters, a and r, have been chosen within the following ranges depending upon the particular technology used: a, 3.0 to 5.0 r, 0.6 to 0.7 Previously the actual parameters have been derived experimentally. However, often an approximation of the pin-to-circuit relation before packaging is desired. To develop such an approximation it is assumed that a machine, its particular technology, and a partitioning algorithm which is expressed as a computer program are known.

Enumeration of strongly connected sequential machines

Recently, attention has been given to the problem of counting the number of equivalence classes of finite automata. The enumeration problem for strongly connected sequential machines has remained unsolved. This paper develops a recursive solution from which the number of strongly connected, complete sequential machines can be determined for an arbitrary state set, input set, and output set.

Delay test effectiveness evaluation of LSSD-based VLSI logic circuits

Delay testing of VLSI logic chips has become critical to the quality of VLSI products. Data from failure analysis showed that small-size defects are more likely to occur than large size defects. These small-size defects are mainly responsible for delay defects that cause potentail system failure (1,2). At chip level, various delay test generation methods were developed (3,4) to consider delay faults either in the gate level or path level. Questions were raised (5,6) concerning the accuracy of the delay test effectiveness evaluation methods used in the conventional approach (7,8). It was shown that defect level, system sensitivity and tester accuracy are major factors in determining the quaIity of delay tests. In other words, a 100 percent delay test coverage obtained from conventional test generators and simulators does not guamntee a sufficient delay test quality.

Necessary and sufficient conditions on conditional probabilities to maximize entropy

Shannon (1948) showed that, by a proper choice of the conditional probabilities of the symbols in a discrete noiseless channel of the finite-state type (which possesses certain inherent constraints), the entropy of symbols on such a channel could be maximized. To date these known sufficient conditions on the conditional probabilities have been assumed to also be the necessary conditions. In this brief paper it is shown that the sufficient conditions as originally stated by Shannon are indeed also the necessary conditions for the range of symbol lengths which are of interest.

Roundtable: logic synthesis in design

No doubt about it, logic synthesis has arrived, or so concludes our panel in this frank discussion of the strengths and weaknesses of actual systems. The roundtable begins with a brief look at the motivation for logic synthesis, continues with commentary on synthesizing control logic versus data flow logic, and then examines current systems and why they succeed.

Design and automation: Designautomation: Design automation system

At the recent ACM 70 Conference, Bob Hitchcock chaired the SIGDA meeting. There were four of us in attendance: Bob (IBM), John Hanne (Texas Instruments), Murray Freeman (Philco), and myself (IBM). Later we caught a passer-by, Bob Brover (UCLA student). Although Bob was not acquainted with SIGDA or its purposes, at our insistence he did come up with a definition of Design Automation (DA). His on-the-spot definition was: DESIGN -- An iterative, decision-making process that seeks to optimize the value of societys resources. AUTOMATION -- Selecting of procedures for doing work with less effort.