Charles J. Varker

The dissolution of fused silica in molten silicon

Abstract Characterization of the dissolution process for fused silica in molten silicon will give a better understanding of the source of oxygen in silicon melts held in crucibles. This letter discusses the surface dissolution rate (1.15 × 10 -5 cm/min). Two other phenomena which were observed are groove formation at the liquid-solid-ambient miniscus due to convective flow and cristobalite crystallization on the silica surface in the presence of the melt.

CHARACTERIZATION OF ELECTRON TRAPS RESULTING FROM OXYGEN PRECIPITATION IN Cz SILICON.

CZ wafers have been heat treated with either a 2 step anneal (16 hrs. @ 800°C/16 hrs. @ 1050°C) or a single step anneal (16 hrs. @ 1050°C). Deep level transient spectroscopy and minority carrier lifetime measurements were obtained on processed wafers containing diode-capacitor arrays. Wafers from the seed end of the crystal (initial oxygen concentration [Oi ~ 40 ppm) with the 2 step anneal showed 2 electron traps E 1 (EC-ET = 0.41 ± 0.02 eV), and E2 (EC-ET = 0.23 ± 0.03 eV), the dominant trap E 1 is shown to correlate with generation lifetime. Wafers implanted with oxygen at 400 keV or 3.5 MeV with doses of 3 X 1015 and 1 X 1016 atoms cm-2 with similar heat treatments reveal electron traps with the same energies as those observed in the unimplanted samples. The high dose samples show a much more complicated spectra, in which E1 and E2 are present. TEM analysis of the seed end unimplanted samples with 2 step anneal show plate type precipitates with punched out loops and dislocations. The tang-end showed octahedral precipitates. The cross sectional view of the implanted samples reveal the precipitates and dislocation loops in a well defined layer. ESR measurements on similar samples with similar anneals reveal residual phosphorus and thermal donors and a new, broad resonance in some of the 2 step annealed samples. This board peak which is not fully analyzed suggests a signature that is not typical of isolated paramagnetic point defects.

Oxygen Precipitation in Silicon - Its Effects on Minority Carrier Recombination and Generation Lifetime

The effects of oxygen precipitation on the minority carrier recombination lifetime (T R ) and the carrier generation lifetime (T G ) have been characterized for a ‘typical’ silicon crystal grown with the Czochralski method. Infrared (IR) absorption measurements were obtained on polished wafers, before and after 2 step thermal anneals at 800°C and 1050°C to characterize the axial distribution of interstitial and precipitated oxygen in the ingot. Computerized measurements on NMOS diode and capacitor arrays were used to characterize the axial and radial distributions of carrier lifetime. The results indicate that oxygen precipitation is the dominant mechanism contributing to the degradation of both minority carrier recombination andgeneration lifetime.

Laser Processing of Ion Implanted Semiconductor Materials for Device Applications

Both pulsed and CW lasers have been used to anneal ion implanted single crystal silicon, polysilicon and ion implanted devices. The advantages and limitations of each type of laser and laser processing in general is discussed. Our results and those in the literature are compared to conventional thermal anneals. The thermal stability of ion-implanted, laser-annealed, single crystal silicon and polysilicon is reported.

Transient Annealing of Boron Implanted Devices

Shallow-junction semiconductor devices have been fabricated using ion implantation and transient annealing with a Varian IA-200 isothermal annealer. Boron implanted diodes, npn bipolar transistors and CMOS ring oscillators have been fabricated and are compared to furnace annealed devices. Boron implanted diodes have been annealed with the RIA and yield acceptably low leakage currents, comparable to furnace annealed devices. The RIA devices have recombination lifetimes of ∼10 μsec. The bipolar transistors subjected to a transient anneal have good base-collector and emitterbase junctions as well as gains of ∼100 in good agreement with the design of the device. MOSFETs and CMOS ring oscillators were fabricated using self-aligned polysilicon gates. The transient annealed devices were equal or superior to devices which were furnace annealed at 800°C for 10 min. The low temperature furnace anneal was necessary to minimize short channel effects. The transient anneal resulted in ring oscillators which were a factor of two faster than furnace samples that were annealed.

Effect of Poly-Si on Electromigration Behaviors and Microstructure Characteristics of Au Metallization

For BJT and MOSFET, poly-Si is the most critical layer used as an emitter to improve the current gain in BJT and as a gate to improve the gate oxide reliability in MOSFET. In both cases, the poly-Si is then connected to the conductor. It is very important to understand how poly-Si affects the microstructure and the electromigration behavior of conductor. NIST test structures (length = 800μ, thickness = 0.7μ, widths = 1, 5, 10 μ) with Au conductor and TiW/TiWN/TiW barrier were used to study the impact of poly-Si. Two groups of samples were used: one with poly-Si under the barrier and the other without poly-Si. Thermal oxide was used to isolate the substrate from the conductor and Si 3 N 4 , was used as passivation. DC stress was performed at 175, 200, and 225°C. Microbeam X-ray Diffraction (μ XRD) was used to characterize the microstructure of the TiW barrier and Au metallization layers as a function of line length and width. The data indicates that samples with poly-Si have lower electromigration resistance for Au conductors for all widths and temperatures, with higher initial deformation fault densities on poly-Si.

An Electrical Characterization of Sol Films Using Devices Formed by Oxygen Implant and Rapid Thermal Processing

The advantages of Silicon-on-Insulator (SO) devices over bulk Silicon devices are well known (speed, radiation hardened, packing density, latch up free CMOS,). In recent years, much effort has been made to form a thin, buried insulating layer just below the active device region. Several approaches are being developed to fabricate such a buried insulating layer. One viable approach is by high dose, high energy oxygen implantation directly into the silicon wafer surface (1-3). With proper implant and annealing conditions, a thin stoichiometric buried oxide with a good crystalline quality silicon overlayer can be formed on which an epitaxial layer can be grown and functional devices and circuits built. As SO1 circuits become market viable, mass production tools and techniques are being developed and evaluated. Of particular interest here is the evaluation of high current oxygen implantation with rapid thermal processing on the electrical characteristics of the oxide-silicon interfaces, the silicon overlayer and the thermally grown oxide on the top surface using measurements on gated diodes and guarded capacitors.