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Dive into the research topics where W. M. Paulson is active.

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Featured researches published by W. M. Paulson.


Journal of Applied Physics | 1998

Ellipsometric determination of optical constants for silicon and thermally grown silicon dioxide via a multi-sample, multi-wavelength, multi-angle investigation

Craig M. Herzinger; B. Johs; William A. McGahan; John A. Woollam; W. M. Paulson

Optical constant spectra for silicon and thermally grown silicon dioxide have been simultaneously determined using variable angle of incidence spectroscopic ellipsometry from 0.75 to 6.5 eV. Spectroscopic ellipsometric data sets acquired at multiple angles of incidence from seven samples with oxide thicknesses from 2 to 350 nm were analyzed using a self-contained multi-sample technique to obtain Kramers–Kronig consistent optical constant spectra. The investigation used a systematic approach utilizing optical models of increasing complexity in order to investigate the need for fitting the thermal SiO2 optical constants and including an interface layer between the silicon and SiO2 in modeling the data. A detailed study was made of parameter correlation effects involving the optical constants used for the interface layer. The resulting thermal silicon dioxide optical constants were shown to be independent of the precise substrate model used, and were found to be approximately 0.4% higher in index than publis...


IEEE Electron Device Letters | 1998

A new SONOS memory using source-side injection for programming

Kuo-Tung Chang; Wei-Ming Chen; Craig T. Swift; Jack Higman; W. M. Paulson; Ko-Min Chang

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications.


Thin Solid Films | 1998

Application of IR variable angle spectroscopic ellipsometry to the determination of free carrier concentration depth profiles

Thomas E. Tiwald; Daniel W. Thompson; John A. Woollam; W. M. Paulson; Robert L. Hance

Abstract Free carrier concentration profiles were determined by Fourier Transform Infrared (FTIR) variable angle spectroscopic ellipsometry. The technique exploits carrier absorption in the mid-infrared spectral range and combines the sensitivity of ellipsometry with a simple Drude free carrier absorption model to determine the carrier profile. In this study, the carrier profiles were modeled as graded multilayers that were constrained to a specific functional form (e.g. Gaussian, complementary error function) when appropriate. Carrier profiles from boron and arsenic ion-implanted that had been subjected to furnace or Rapid Thermal Annealing (RTA) annealed silicon wafers were compared to Spreading Resistance Probe and Secondary Ion Mass Spectrometry profiles. p−p+doped epitaxial silicon samples (before and after annealing) were also measured and the results were compared to theory.


Journal of Applied Physics | 1977

Interdiffusion in composition‐modulated copper‐gold thin films

W. M. Paulson; J. E. Hilliard

Vapor‐deposited Cu‐Au thin films were produced containing composition modulations with wavelengths between 8 and 26 A. The modulations produced satellite peaks in the x‐ray diffraction patterns. Amplification factors and the corresponding diffusion coefficients were obtained by measuring the decay rate of the satellite intensities. The amplification factor reached a maximum at 17 A and decreased at both shorter and longer wavelengths. Interdiffusion coefficients between 10−21 and 10−19 cm2/sec were measured over the temperature range 200–260 °C. The effective diffusion coefficient is linearly dependent on the function B2(λ) for λ≳10 A. From the wavelength dependence of the measured diffusivities, a gradient‐energy coefficient of −4.7×10−6 erg/cm was obtained and is in good agreement with theoretical estimates. These experimental results were compared with the predictions from a proposed model for diffusion on cubic lattices.


Journal of Applied Physics | 1984

Rapid isothermal annealing of As-, P-, and B-implanted silicon

S. R. Wilson; W. M. Paulson; R. B. Gregory; A. H. Hamdi; F.D. McDaniel

Single‐crystal silicon wafers have been implanted with As, P, and B to doses of 1×1013–1×1016/cm2 and given a transient anneal using a Varian IA‐200 Rapid Isothermal Annealer. The system uses infrared radiation to heat the wafers to temperatures in excess of 1000 °C for times on the order of 10 sec. Sheet resistance and Hall measurements have been used to determine the effect of the anneal on the electrical properties of the wafers. Rutherford backscattering and secondary ion mass spectroscopy have been used to measure lattice damage and dopant profiles before and after annealing. As and P are lost during the anneal unless the wafer is capped. Complete activation can be achieved with very little dopant diffusion. Residual damage is minimal in (100) oriented wafers that had been implanted with As. However, for (111) wafers damage is less in (111) wafers implanted to doses ≥5.0×1015/cm2, than in (111) wafers implanted to doses ≤5.0×1015/cm2. The diffusion of As during this transient anneal has been modeled ...


Journal of Applied Physics | 1979

The pulse‐degradation characteristic of ZnO varistors

C. G. Shirley; W. M. Paulson

We find that two factors bear on the high‐energy pulse degradation of a varistor’s electronic characteristic. First, the electronic structure of active grain‐boundary segments depends solely on the peak temperature occurring there during a pulse, and second, this peak temperature is determined by the thermal transport properties of the microstructure. We find that the intrinsic electronic structure can be modified without changing the microstructure to greatly improve the pulse‐degradation performance of a varistor by an anneal at low temperature (600 °C) in oxygen. The influence of microstructure is embodied in the grain‐boundary temperature‐magnification factor Zgb which is defined, measured, and studied theoretically. Theory shows that there are three regimes: (i) a long‐pulse‐width regime where Zgb=1, (ii) a short‐pulse‐width regime where Zgb∼ (pulse width)−1/2, independent of pulse energy, and (iii) a very‐short‐pulse‐width (or high‐energy‐density) regime where Zgb∼ (pulse energy)−1/2, independent of...


Applied Physics Letters | 1982

Rapid isothermal anneal of 75As implanted silicon

S. R. Wilson; Richard B. Gregory; W. M. Paulson; A. H. Hamdi; F.D. McDaniel

Silicon wafers implanted with 75As have been annealed with a Varian IA‐200 isothermal annealer. The anneal occurs in vacuum using radiation from a resistively heated sheet of graphite. The anneal quality depends on the graphite heater temperature and exposure time. If the anneal time is too short implantation damage remains and if the time is too long measurable losses of As occur causing the sheet resistance to increase. The loss of As can be prevented by depositing 0.05 μm of SiO2 on the wafer before annealing.


IEEE Transactions on Electron Devices | 1992

A high-performance 0.5- mu m BiCMOS technology for fast 4-Mb SRAMs

James D. Hayden; Thomas C. Mele; Asanga H. Perera; David Burnett; F. W. Walczyk; Craig S. Lage; Frank K. Baker; Michael Woo; W. M. Paulson; M. Lien; Yee-Chaung See; Dean J. Denning; Stephen J. Cosentino

A high-performance 0.5- mu m BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 mu m/sup 2/ by creating self-aligned bit-sense and V/sub ss/ contacts. A WSi/sub x/ polycide emitter n-p-n transistor with an emitter area of 0.8*2.4 mu m/sup 2/ provides a peak cutoff frequency (f/sub T/) of 14 GHz with a collector-emitter breakdown voltage (BV/sub CFO/) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f/sub T/ and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process. >


Applied Physics Letters | 1984

Grain growth during transient annealing of As‐implanted polycrystalline silicon films

S. J. Krause; S. R. Wilson; W. M. Paulson; R. B. Gregory

Polycrystalline silicon films deposited on oxidized wafer surfaces were implanted with As and annealed on a Varian IA‐200 rapid thermal annealer. The effects of annealing conditions on resultant grain size of original as‐deposited columnar grains are presented with a modified model for interfacially driven grain growth. During an initial temperature rise to 910 °C the original grain size (39 nm) and dopant profile are not significantly altered. At 1145 °C the grains have grown to 90 nm and the As is uniformly distributed throughout the film. Additional annealing to 1300 °C in 20 s causes grains to grow to 260 nm. Further grain growth is retarded due to the 300‐nm film thickness. During annealing of unencapsulated films a substantial loss of As results in a lower rate of grain growth. When grain size increases, Hall mobility increases and resistivity decreases.


Microelectronics Reliability | 1980

Chip corrosion in plastic packages

Howard M. Berg; W. M. Paulson

Abstract The corrosion performance of both unencapsulated and plastic encapsulated parts has been studied under temperature-humidity-bias (THB) stresses using a patterned test chip with aluminum metallization. The effect of encapsulation materials and ionic contaminants purposely introduced on the chip surface has been determined for both accelerated THB and severe, real life conditions. Unencapsulated test chips exhibited very different THB performance characteristics from encapsulated parts including a near-zero induction time and a shallow post-induction slope on the % failures vs time curve. The induction time and mean-time-to-failure (MTF) for encapsulated devices were strong functions of both the polymeric class of encapsulant and the particular compound employed. At least part of the difference in performance between molding compounds has been attributed to impurities inherent in the compounds. Impurities contributed from conductive epoxies used for die attach also adversely affect the devices MTF, as do normal contaminants present on as-plated leadframes. The environmental factors of temperature, relative humidity and bias greatly affect the performance of encapsulated devices. In this study, the MTF decreased dramatically with bias between 5 and 30 volts, the range over which most devices operate. The acceleration factors relating device performance in an 85°C/85%RH environment to severe, real life conditions were surprisingly small and somewhat dependent on the encapsulant.

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A. H. Hamdi

University of North Texas

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F.D. McDaniel

University of North Texas

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