Charles Philip Roth

A programmer's view of performance monitoring in the PowerPC microprocessor

Performance monitor (PM) support in on-chip PowerPC® microprocessors is used to analyze processor, software, and system attributes for a variety of workloads. The interface to the PowerPC 604® microprocessor, which we abbreviate “604,” has been externalized to end users. We discuss the enhanced PM support available in an upgrade of the 604, the PowerPC 604e™ microprocessor, which we abbreviate “604e.” We discuss the challenges related to the externalization of the PM support as it relates to other PowerPC processors not derived from the 604 and briefly contrast these PMs with other PMs. We also describe an application programming interface (API) to the on-chip PM support, its design methodology, and its usage considerations, intended to meet these challenges.

Performance monitoring on the PowerPC 604 microprocessor

Performance monitors (PM) have been traditionally viewed as hardware luxuries only available to large/multichip processors. This perception is quickly changing thanks to the incorporation of monitoring instrumentation in most of the current high-volume microprocessors used in PCs and workstations. The PowerPC 604 uP has raised the standard of excellence in this area. It provides a wealth of very advanced features for analyzing system hardware, software, and symmetric multiprocessor systems. These capabilities are becoming indispensable as more function is moved from the system boards to the microprocessors. Furthermore, the PowerPC 604 is enhancing the effort of porting software between various architectures. Software vendors to system architects are currently taking advantage of these PowerPC 604 performance monitor capabilities with great success. Some of these companies include IBM, Apple, Motorola, Groupe Bull, and Microsoft among others.

Load miss performance analysis methodology using the PowerPC 604 performance monitor for OLTP workloads

This paper describes a methodology via which the PowerPC 604 Micro Processor (abbreviated 604 in the remainder of this paper) performance monitor can be used to examine and contrast the effects of hardware variations on system performance. We present performance measurement data and analysis of an On-Line Transaction Processing (OLTP) workload, which are derived via repeated runs using a database software engine with several different memory and processor speeds. We show for our workload that variations in the easily measured load miss sojourn can be used to approximate the valuable but difficult to measure composite cache miss penalty. We also show interesting variations in bus utilization versus bus to processor clock ratios.

The PowerPC 604 microprocessor design methodology

The PowerPC 604 microprocessor design methodology represents an interesting evolution from the one used to produce the PowerPC 601 /spl mu/P. While the PowerPC 601 /spl mu/P was intended to provide a marketable PowerPC product as quickly as possible, the PowerPC 604 /spl mu/P had a higher performance implementation goal. We feel that our design techniques were appropriate for this new balance of schedule and performance. New challenges included more reliance on custom circuits and a larger amount of design data than we had previously dealt with. This required expanding our design process to include tools from Cadence, Motorola, and IBM. The PowerPC 604 /spl mu/P used synthesis to transform the model to a gate-level implementation and billions of cycles were simulated to ensure compliance with the PowerPC instruction set. The use of this design methodology has led to successful first pass silicon.<<ETX>>

Divide and conquer approach to functional verification of PowerPC/sup TM/ microprocessors

Design verification engineers are one of the hottest commodities in microprocessor design. The increased complexity of these chips has nor been accompanied by an equal increase in design verification techniques. Thus, the existing workforce must work smarter in order to make up the difference. This paper outlines one of the areas in which verification engineers at the Somerset Design Center have been able to do just that. By taking blocks of designs that have been entered early, and creating a unit-level simulation environment, the authors are able to do large amounts of testing (sometimes exhaustive) before the whole chip has been designed. This has contributed significantly to cutting down the time it takes to run functional simulations for the whole chip, since most of the problems found at this point are interface problems. The test cases created for the unit-level simulations are then re-run at the chip level in order to provide full confidence of quality. Although it is hard to exactly quantify the total impact on the time-to-market of any product, it is evident that the described techniques save resources and time.