Edward Hugh Welbon

Performance monitoring on the PowerPC 604 microprocessor

Performance monitors (PM) have been traditionally viewed as hardware luxuries only available to large/multichip processors. This perception is quickly changing thanks to the incorporation of monitoring instrumentation in most of the current high-volume microprocessors used in PCs and workstations. The PowerPC 604 uP has raised the standard of excellence in this area. It provides a wealth of very advanced features for analyzing system hardware, software, and symmetric multiprocessor systems. These capabilities are becoming indispensable as more function is moved from the system boards to the microprocessors. Furthermore, the PowerPC 604 is enhancing the effort of porting software between various architectures. Software vendors to system architects are currently taking advantage of these PowerPC 604 performance monitor capabilities with great success. Some of these companies include IBM, Apple, Motorola, Groupe Bull, and Microsoft among others.

Load miss performance analysis methodology using the PowerPC 604 performance monitor for OLTP workloads

This paper describes a methodology via which the PowerPC 604 Micro Processor (abbreviated 604 in the remainder of this paper) performance monitor can be used to examine and contrast the effects of hardware variations on system performance. We present performance measurement data and analysis of an On-Line Transaction Processing (OLTP) workload, which are derived via repeated runs using a database software engine with several different memory and processor speeds. We show for our workload that variations in the easily measured load miss sojourn can be used to approximate the valuable but difficult to measure composite cache miss penalty. We also show interesting variations in bus utilization versus bus to processor clock ratios.

POWER2: performance measurement and analysis of TPC-C

This paper discusses the implementation and features of the POWER2 systems embedded hardware performance monitor, describes its application to the analysis of the behavior of the Transaction Processing Performance Councils TPC-C benchmark on the POWER2 CPU, simulating an on-line transaction processing (OLTP) workload, and summarizes the results of the analysis. The POWER2 performance monitor provides hardware measures that are important to software developers tuning the operating system and application software, as well as to system designers responsible for the development of new systems. The measures characterize storage system performance and compiler instruction scheduling opportunity, both critical to good system performance.<<ETX>>