Charles R. Erickson

Third-generation architecture boosts speed and density of field-programmable gate arrays

Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices. The architecture was devised to allow complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. This architecture is described. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.<<ETX>>

A novel predictable segmented FPGA routing architecture

In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.