William S. Carter

Third-generation architecture boosts speed and density of field-programmable gate arrays

Using a combination of architectural and process improvements, a third-generation family of field-programmable gate arrays (FPGAs) features up to twice the density and speed of currently-available FPGA devices. The architecture was devised to allow complete and efficient automated design implementation of FPGA-based designs, as well as maximum density and performance. This architecture is described. User-configurable on-chip static memory resources further contribute to the high integration levels available to users of the third-generation devices.<<ETX>>

The future of programmable logic and its impact on digital system design

Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device. Already a mainstream logic technology, the growth rate of FPGA usage will continue to exceed that of other ASIC technologies. FPGA technology is having a major impact on electronic system design, especially through the use of FPGAs as reconfigurable computing elements.<<ETX>>

A 9000-gate user-programmable gate array

The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources. Configuration is established by programming internal static memory cells that determine the logic functions and interconnections. An IC design and layout methodology based on modularity combined with the use of advanced processing technology allowed this architecture to be extended to 9000 usable gates. Architectural resources were designed to allow for a range of logic densities without compromising overall performance. User-programmable gate arrays can be used in place of conventional, mask-programmed gate arrays for the majority of digital designs.<<ETX>>