Charlotte Drazek

High Performance Mixed Signal and RF Circuits Enabled by the Direct Monolithic Heterogeneous Integration of GaN HEMTs and Si CMOS on a Silicon Substrate

In this work we present recent results on the direct heterogeneous integration of GaN HEMTs and Si CMOS on a silicon substrate. GaN HEMTs whose DC and RF performance are comparable to GaN HEMTs on SiC substrates have been achieved. As a demonstration vehicle we designed and fabricated a GaN amplifier with pMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects. This simple demonstration circuit is a building block for more advanced RF, mixed signal and power conditioning circuits, such as reconfigurable or linearized PAs with in-situ adaptive bias control, high power digital-to-analog converters (DACs), driver stages for on-wafer optoelectronics, and on-chip power distribution networks.

A high performance differential amplifier through the direct monolithic integration of InP HBTs and Si CMOS on silicon substrates

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. InP HBTs (0.5 × 5 um2 emitter) with ft and fmax ≫ 200GHz were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). A BCB based multilayer interconnect process was used to interconnect the InP HBT and Si CMOS to create a differential amplifier demonstration circuit. The heterogeneously integrated differential amplifier serves as the building block for high speed, low power dissipation mixed signal circuits such as ADCs and DACs.

New Efficiency Frontiers with Wafer-Bonded Multi-Junction Solar Cells.

Triple-junction (3J) solar cells will soon be history. The next generation of multi-junction (MJ) devices are now reaching efficiencies far beyond the record levels of 3J cells on Germanium. In this paper we present results of a 4J wafer-bonded solar cell with bandgaps 1.88 / 1.45 // 1.10 / 0.73 eV measured with an improved efficiency of 46.5% at 324x by Fraunhofer ISE. Design for cost has, from the outset, been a priority with the development of engineered substrates to replace costly and low yielding InP substrates, a product building on Soitec’s proprietary SmartCut technology. Wafer bonding enables the electro-mechanical combination of lattice and thermal expansion mismatched materials with electrically conductive, transparent bonds, enabling concentrator solar cells to be built from high quality 2J GaInP/GaAs absorbers lattice-matched to GaAs bonded to high quality 2J GaInPAs/GaInAs absorbers lattice matched to InP that operate well at high concentration.

Four-Junction Wafer-Bonded Concentrator Solar Cells

The highest solar cell conversion efficiencies are achieved with four-junction devices under concentrated sunlight illumination. Different cell architectures are under development, all targeting an ideal bandgap combination close to 1.9, 1.4, 1.0, and 0.7 eV. Wafer bonding is used in this work to combine materials with a significant lattice mismatch. Three cell architectures are presented using the same two top junctions of GaInP/GaAs but different infrared absorbers based on Germanium, GaSb, or GaInAs on InP. The modeled efficiency potential at 500 suns is in the range of 49-54% for all three devices, but the highest efficiency is expected for the InP-based cell. An efficiency of 46% at 508 suns was already measured by AIST in Japan for a GaInP/GaAs//GaInAsP/GaInAs solar cell and represents the highest independently confirmed efficiency today. Solar cells on Ge and GaSb are in the development phase at Fraunhofer ISE, and the first demonstration of functional devices is presented in this paper.

Challenges and Progress in Germanium-on-Insulator Materials and Device Development towards ULSI Integration

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

Development of high efficiency wafer bonded 4-junction solar cells for concentrator photovoltaic applications

The next generation of multi-junction concentrator solar cells will have to reach higher efficiencies than todays devices. At the same time these solar cells must be reliable in the field, be manufacturable with good yield and at sufficiently low cost. Inevitably the request of higher efficiency requires four or even more junction devices. A four-junction solar cell combination of GaInP/GaAs//GaInAsP/GaInAs with bandgap energies of 1.9, 1.4, 1.1, 0.7 eV is developed in a close collaboration between the Fraunhofer ISE, Soitec, CEA-LETI and HZB. This 4-junction cell hits close to the optimum of theoretical efficiency contour plots and has the potential to reach efficiencies up to 50 % under concentration. Challenges are associated with lattice-mismatch between GaAs and InP which is overcome by direct wafer-bonding. The high cost of the InP is addressed by the use of engineered substrates which only require a 500 nm thin mono-crystalline InP layer instead of several hundred μm. Excellent solar cell results up to 44.7 % efficiency have been obtained under concentration for devices manufactured on InP bulk substrates. The high cell efficiency is also supported by out-door characterization of one cell below a Fresnel lens with 16 cm2 aperture area. 38.5 % conversion efficiency has been measured for this mono-module in Freiburg under real operating conditions without any corrections.

Wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cells

Multiple-junction solar cells made from III-V compound semiconductors are delivering the highest solar-electric conversion efficiencies. Increasing the number of junctions offers the potential to reach higher efficiencies. Direct wafer bonding offers a unique opportunity to combine lattice mismatched materials through a permanent, electrically conductive and optically transparent interface. In addition, the use of Smart Cut ™ technology, associated with its material recycling capabilities allows from a cost perspective the use of expensive bulk material such as InP. Combination of both technologies opens new opportunities to deliver cost effective high efficiency solar cells. In this respect, we have been able to demonstrate a record efficiency of 44,7% with a wafer bonded 4-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cell with bandgap energies of 1.88/1.44//1.11/0.70 eV respectively. The bandgaps are chosen to be close to optimal for conversion under concentrated sunlight [1]. This paper prese...

SiGe and Ge on Insulator Wafers

Since 90nm technology Germanium (Ge) element has become increasingly popular in the CMOS processing for enhancing transistor performance, especially enhancing hole mobility for P-type transistors. The main driver has been the embedded SiGe in the source/drain region and its extraordinary boost on PFET drive current [1]. More recently Ge has enabled band engineering with respect to Silicon for Vt tuning [2,3] in addition to channel engineering for mobility enhancement. Looking into the future the need for SiGe alloys or pure Ge is increasing, as it is contemplated as a seed for IIIV material growth [4], or even the replacement of Si by Ge in the channel to take advantage of the high electron and hole mobilities [5]. Today the manufacturing reality shows us that all Ge needs can be fulfilled by epitaxy during the processing of the devices [6]. In this paper we will introduce the Dual Channel substrate having a strained SiGe layer grown on top of a SOI substrate. Starting with this wafer and thru condensation process one can produce a uniform SiGe layer suitable for Fully Depleted applications.

Progress and challenges in the direct monolithic integration of III–V devices and Si CMOS on silicon substrates

We present results on the direct monolithic integration of III–V devices and Si CMOS on a silicon substrate. Through optimization of device fabrication and material growth processes III–V devices with electrical performance comparable to devices grown on native III–V substrates were grown directly in windows adjacent to CMOS transistors on silicon template wafers or SOLES (Silicon on Lattices Engineered Substrates). While the results presented here are for InP HBTs, our direct heterogeneously integration approach is equally applicable to other III–V electronic (FETs, HEMTs) and opto-electronic (photodiodes, VSCLS) devices and opens the door to a new class of highly integrated, high performance, mixed signal circuits.

InP-based composite substrates for four junction concentrator solar cells

A photovoltaics conversion efficiency of 46% at 508 suns concentration was recently demonstrated with a four-junction solar cell consisting in a GaAs-based top tandem cell transferred onto an InP-based bottom tandem cell, by means of wafer bonding. We have successfully produced and characterized different InPOS (for InP-On-Substrate) composite substrates, that could advantageously replace fragile and expensive InP bulk wafers for the growth of the bottom tandem cell. The InPOS composite substrates include a thin top InP layer with thickness below 1µm, transferred onto a host substrate using the Smart Cut™ layer transfer technology. We developed InP-On-GaAs, InP-On-Ge and InP-On-Sapphire substrates with surface and crystal qualities similar to the InP bulk ones. A low electrical resistance of 1.4mΩ.cm² was measured along the InP transferred layer and the bonding interface. An epitaxial bottom tandem cell was grown on an InPOS substrate, and the corresponding PL behavior was found identical to that of cells...