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Dive into the research topics where Charlotte Gillot is active.

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Featured researches published by Charlotte Gillot.


Proceedings of the IEEE | 2009

System on Wafer: A New Silicon Concept in SiP

Gilles Poupon; N. Sillon; David Henry; Charlotte Gillot; Alan Mathewson; L. Di Cioccio; Barbara Charlet; Patrick Leduc; Maud Vinet; Perrine Batude

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.


ieee industry applications society annual meeting | 2000

Double-sided cooling for high power IGBT modules using flip chip technology

Charlotte Gillot; C. Schaeffer; R. Ferret; C. Massit; Meysene

A new technique for the packaging of IGBT modules has been developed. The components are sandwiched between two DBC (direct bond copper) substrates with aluminum nitride. Wire bonds are replaced with flip chip solder bumps, which allows to cool components on both sides. Microchannel heat sinks are directly integrated in the package to decrease the thermal resistance of the module. Thus, a very compact module with high thermal performance is obtained. A prototype with two IGBTs (insulated gate bipolar transistor) and four diodes associated in parallel was realised and tested. In this paper, the innovative packaging technique is described, and results of thermal tests are presented.


ieee industry applications society annual meeting | 1999

A new packaging technique for power multichip modules

Charlotte Gillot; D. Henry; C. Schaeffer; C. Massit

A new packaging technique for power multichip modules has been developed. The components are sandwiched between two DBC (direct bond copper) substrates with aluminum nitride. This innovative technique allows to replace wire bond with flip chip and to cool the module on both sides. Thus, electrical, thermal and reliability performance can be improved.


ieee industry applications society annual meeting | 1997

Integrated single and two-phase micro heat sinks under IGBT chips

Charlotte Gillot; Luc Meysenc; Christian Schaeffer; Alain Bricard

Experiments have been performed to assess the feasibility of single and two-phase micro heat exchangers applied to the cooling of IGBT power components. After a brief recall of the principal characteristics of such heat exchangers, prototypes that have been built and tested are described. Experimental measurements are then compared to the predictions of the thermal and hydraulic performances with water and the inert fluorocarbon liquid (FC72) as coolant fluids.


ECTC | 2011

Gold-tin bonding for 200mm wafer level hermetic MEMS packaging

Arnaud Garnier; Emmanuelle Lagoutte; Xavier Baillin; Charlotte Gillot; Nicolas Sillon


Archive | 2012

Method for producing a structure with a cavity sealed hermetically under a controlled atmosphere

Jean-Louis Pornin; Xavier Baillin; Charlotte Gillot; Laurent Vandroux


Proceedings of the IEEE | 2009

System on Wafer: A New Silicon Concept in SiP : With this flexible, low-cost, high-yield packaging technique, which can be implemented by various technologies, components and chips are mounted on a silicon wafer

Gilles Poupon; Nicolas Sillon; David Henry; Charlotte Gillot; Alan Mathewson; Lea Di Cioccio; Barbara Charlet; Patrick Leduc; Maud Vinet; Perrine Batude


Techniques de l'ingénieur. L'Entreprise industrielle | 2004

Caloducs plats en silicium pour composants électroniques

Yvan Avenas; Charlotte Gillot; Christian Schaeffer


Houille Blanche-revue Internationale De L Eau | 2003

Conception et realisation d'un caloduc plat a rainures en silicium

Charlotte Gillot; Gilles Poupon; Yvan Avenas; Christian Schaeffer; Elise Fournier


Houille Blanche-revue Internationale De L Eau | 2003

Conception et ralisation d'un caloduc plat rainures en silicium

Charlotte Gillot; Gilles Poupon; Yvan Avenas; Christian Schaeffer; Elise Fournier

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Alan Mathewson

Tyndall National Institute

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Yvan Avenas

École nationale supérieure d'ingénieurs électriciens de Grenoble

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