Patrick Leduc

Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

Through Silicon Via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more and more mandatory. In this paper, a full parametric and frequency dependent model of high aspect ratio TSV is proposed based on both electromagnetic (EM) simulations and RF measurements. This model enables to extract TSV resistance, self inductance, oxide capacitance and parasitic elements due to the finite substrate resistivity. Its full compatibility with SPICE solvers allows the investigation of TSV impact on circuit performance.

Enabling technologies for 3D integration: From packaging miniaturization to advanced stacked ICs

This paper presents an overview of current 3D technologies development at CEA/LETI Minatec. Three different 3D approaches are described, and can be seen as 3 generations for that emerging field. An original through silicon via (TSV) process for CMOS image sensors (CIS) is presented, and electrical results showing very low resistances and high yields are described. A similar TSV process, combined with temporary bonding and low pitch interconnects is used to address the second generation of 3D integration, the active silicon interposer. A first demonstrator of a TSV process on thin wafer is described. Some reliability results on an innovative technology for flip chip, fully compatible with chip stacking, are detailed. It will also be shown that by developing advanced technology like direct bonding and high density TSV, CEA-Leti is also preparing ultimate 3D integration, with very high density interconnects.

Enabling technologies for 3D chip stacking

This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter-strata connection pitch lower than 10 mum. Direct bonding technology, die-to-wafer self-assembly, wafer thinning process and copper TSV process are discussed. 2 mum to 5 mum large copper TSV chains are presented with a TSV resistance <200 mOmega. Substrate noise due to TSV is also considered by TCAD and SPICE simulations in order to define preliminary design rules.

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.

Enabling 3D interconnects with metal direct bonding

This paper presents the implementation of a key technology developed for high density 3-D integration by circuit stacking. Direct copper bonding at room temperature, atmospheric pressure and ambient air of copper pads allowed the elaboration of a 10×10 9m vertical interconnect with a contact resistance of 10 mohms. First tests on tungsten bonding will be also reviewed.

First integration of Cu TSV using die-to-wafer direct bonding and planarization

Copper-filled Through-Si Vias (TSV) with diameters from 2 µm to 5 µm have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400°C. This demonstration is the first step to validate the industrial compatibility between high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mOhm and a capacitance of about 30 fF, 3 µm-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs.

An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling

An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low stress high deposition rate oxide is deposited to embed the dices. A final thinning is then done to recover a flat and smooth surface before the trough silicon vias

Understanding CMP-induced delamination in ultra low-k/Cu integration

In-situ friction characterization during chemical-mechanical polishing (CMP) was investigated to understand delamination mechanisms of a porous ultra low-k (ULK)/Cu stack. By quantifying the delaminated area within the wafer, it was shown that adhesion failure is driven by the work done against the CMP-induced friction force, and is correlated to the adhesion strength of the weakest interface. A low-stress CMP was successfully achieved on a first level of ULK/Cu interconnects having a low adhesion SiC/ULK interface (Gc=1.3 J/m/sup 2/) and a porous dielectric material with low mechanical properties (Youngs modulus E=3.5 GPa, hardness H=0.7 GPa).

Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking

Evaluation of Through Silicon Via (TSV) electrical performance is hardly required today to improve heterogeneous 3D chip performance in the frame of a “more than Moore” approach. Accurate modeling of TSV is consequently essential to perform design optimizations and process tuning. This paper proposes a methodology based on RF characterizations and simulations, leading to a frequency dependent analytical model including MOS effect of high aspect ratio TSV. Specific test structures integrated on both floating Si bulk and CMOS 65 nm active wafers according to a face-to-face Via Last After Bonding process enable C(V) and RF measurements. TSV equivalent model including all substrate effects is proposed according to CMOS 65 nm specificities (voltage, frequency, dimensions and Si conductivity) and implemented in SPICE simulator to predict TSV impact on signal propagation.

Characterization and modelling of Si-substrate noise induced by RF signal propagating in TSV of 3D-IC stack

TSVs in 3D integrated circuits are a source of noise that can affect nearby transistor performance. So an analytical physics-based model of the TSV-to-substrate coupling is proposed to perform time domain or noise simulations. Silicon measurements at low frequencies and radiofrequencies are reported. Simulations are done using a software performing device and electromagnetic co-simulations. The model and simulations are validated by measurements. Simulations to study the sensitivity of the TSV structure to the layout show changes in the TSV-to-substrate coupling behavior.