Chen Guanghua

A fast variable-length decoder with optimized lookup tables on FPGA [MPEG applications]

A novel high performance variable-length code (VLC) decoder for MPEG applications is proposed. It has higher throughput and requires smaller memory resources by group matching and lookup table optimization. Group matching is developed to simplify matching procedure and reduce the process time. Group recombination, group decomposition and group properties are applied to optimize the lookup tables, which removes the redundant bits and reduces the implementation complexity. This decoder is implemented on FPGA and the throughput is about 55 Msymbols/s at 55 MHz clock rate.

An LED Driver Using Joint Frequency-Pulse Width Modulation Scheme

In order to provide LCD backlighting with multiple strings of LEDs, an LED driver using the joint frequency-pulse width modulation scheme is proposed in the paper. A PWM signal is generated by the Pulse Width Modulation (PWM) module in MCU chip, which is used to drive a DC-DC boost converter for LED power. The voltage and current of the boost circuit, along with all the channels current of LED, are measured by the Analog Digital Converter (ADC) module in MCU chip, which are used to adjust the voltage of the boost circuit and supply comprehensive protection for the LED driver. To minimize the step size of the output voltage, the joint frequency-pulse width modulation scheme is proposed to regulate the output voltage of the boost circuit to an ideal value in the range of error, which increases the efficiency of the power. To reduce the crossover power dissipation of the MOSFET switch, the MOSFET driver is designed to charge or discharge the gate with big drive current capability, which can reduce the time of MOSFET to be turned on and off efficiently. The measurement results show that the LED driver is extremely efficient and steady, the maximum step size of the output voltage is less than 0.3V, and the conversion efficiency of the DC-DC converter is up to 94%. Thus the LED driver not only meets the demand of the parameter of LED, but also has high cost performance.

Fast Computation of Wigner-Ville Distribution

The paper proposes a new method for computation of the Wigner-Ville distribution(WVD) taking account of the conjugate symmetry of the WVD kernel function and the periodicity and symmetry of the trigonometric function. The method transfers the computation of WVD into real field from complex field to remove the redundancies in the fast Fourier transform(FFT) computation. The realization of fast cosine operation and fast sine operation considerably reduces the computation cost. Theoretical analysis shows that the algorithm provided in the paper is much more advantageous than the existed ones.

VLSI Implementation of CAVLC Decoder for H.264/AVC Video Decoding

This paper presents an efficient method of the contest- based adaptive variable length code (CAVLC) decoder for H.264/AVC standard. In the proposed design, according to the regularity of the codewords, the first 1 detector is used to solve the problem that the traditional method of table- searching has low efficiency. Considering the relevance of the data used in the process of RunBefores decoding, arithmetic operation is combined with FSM, which achieves higher decoding efficiency. The simulation result shows that the decoder can decode the coded stream of transform coefficients in each block. Moreover, it can decode every syntax element in one clock cycle. When the proposed design is synthesized at clock constraint of 100 MHz, the synthesis result shows that the design costs 9600 cells under a 0.25 mum CMOS technology, which meets the demand of real time decoding in H.264/AVC standard.

An improved method of endpoints detection based on energy-frequency-value

It is very important to detect the speech endpoints accurately in speech recognition. This paper presents an improved method of endpoints detection based on the product of energy and frequency. The method uses energy-frequency-value as threshold to detect endpoints of speech signal, and induces the upper limit of length threshold and the lower limit of length threshold of speech signal, so that the improved method can detect speech endpoints by adapting the threshold to the strength of background noise automatically. The simulation results show that the method is more accurate and more anti-noise than the traditional one based on energy and frequency

VLSI Implementation of Sub-pixel Interpolator for H.264/AVC Encoder

The design of H.264/AVC interpolation unit is very challenging for the high memory bandwidth and large calculation complexity caused by the new coding features of variable block size (VBS) and 6-tap filter. In this paper, a novel one-step interpolation implementation algorithm is proposed which can effectively reduce processing cycle because of its less memory accessing. Moreover, a data reuse scheme is used to save processing cycle and memory bandwidth. A high performance hardware architecture is implemented according to the methods mentioned above. As a result, 26% memory bandwidth reduction and 45% processing cycle reduction are achieved, which shows that our architecture is an efficient hardware accelerating solution and can be used in real-time encoder.

The Wigner-Ville Distribution and the Cross Wigner-Ville Distribution of Noisy Signals

The Wigner-Ville distribution (WVD) and the cross Wigner-Ville distribution (XWVD) have been shown to be efficient in the estimation of instantaneous frequency (IF). But the statistical result of the IF estimation from XWVD peak is much better than using WVD peak. The reason is given in the paper from a statistical point of view. Theoretical studies show that XWVD of the analyzed signal can be estimated from XWVD of the noise-contaminated signal. The estimation is unbiased, and the variance is equal to that of noise. In this case, WVD cannot be estimated from WVD of the noise-contaminated signal. Therefore higher SNR is required when WVD is used to analyze signals

A High-Speed Memory Interface Architecture for MPEG2 Video Decoder

Motion compensation (MC) routines of MPEG-2 MP@HL video decoding intensively access the video data stored in external memory, thus efficient memory access is critical in the design of decoder chip. In this paper, an advanced architecture of MC is proposed to perform different types of picture prediction modes employed by the MPEG-2 standard and an address translation method is developed for memory interface. In order to relieve the burden of MC, four pixel generators are used to execute bi-prediction and half-pel precision in parallel. Image data fetched from the external frame memory are reused, so that a great amount of frame memory access can be reduced. The features of SDRAM and the fact that all types of MC algorithm have regular memory access patterns are exploited to minimize the number of overhead cycles needed for row activations in array address translation. Compared with the conventional linear translation, array address translation can reduce most of the row activations. The proposed architecture is very effective not only for increasing the speed of memory access but also for improving the performance of MC

VLSI implementation of CAVLC decoder with power Optimized for H.264/AVC video decoding

This paper presents an efficient method of the contest-based adaptive variable length code (CAVLC) decoder with power Optimized for H.264/AVC standard. In the proposed design, according to the regularity of the codewords, the first 1 detector is used to solve the problem that the traditional method of table-searching has low efficiency and high power dissipation. Considering the relevance of the data used in the process of RunBeforepsilas decoding, arithmetic operation is combined with FSM, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in module level and register level respectively, which reduce 43% dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at clock constraint of 100 MHz, the synthesis result shows that the design costs 11300 gates under a 0.25 um CMOS technology, which meets the demand of real time decoding in H.264/AVC standard.

Wigner-Ville distribution and cross Wigner-Ville distribution of noisy signals

Abstract The Wigner-Ville distribution (WVD) and the cross Wigner-Ville distribution (XWVD) have been shown to be efficient in the estimation of instantaneous frequency (IF). But the statistical result of the IF estimation from XWVD peak is much better than using WVD peak. The reason is given from a statistical point of view. Theoretical studies show that XWVD of the analyzed signal can be estimated from XWVD of the noise-contaminated signal. The estimation is unbiased, and the variance is equal to that of noise. In this case, WVD cannot be estimated from WVD of the noise-contaminated signal. Therefore, higher SNR is required when WVD is used to analyze signals.