Chen Guangju

Wavelet neural network based fault diagnosis in nonlinear analog circuits

Abstract The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studied Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation(BP) neural network Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.

Feature evaluation and extraction based on neural network in analog circuit fault diagnosis

Abstract Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis effciency. A fault diagnosis illustration validated this method.

Anti-aliasing nonstationary signals detecion algorithm based on interpolation in the frequency domain using the short time Fourier transform

To eliminate the aliasing that appeared during the measurement of multi-components nonstationary signals, a novel kind of anti-aliasing algorithm based on the short time Fourier transform (STFT) is brought forward. First the physical essence of aliasing that occurs is analyzed; second the interpolation algorithm model is setup based on the Hamming window; then the fast implementation of the algorithm using the Newton iteration method is given. Using the numerical simulation the feasibility of algorithm is validated. Finally, the electrical circuit experiment shows the practicality of the algorithm in the electrical engineering.

A modeling and performance evaluation method about the parallel multi-task radar automatic test system

The structure of the test system gets more complicated, the test tasks increases in number, and the relations between them are stronger. So, the traditional establish method of the test system relying on peoples experiences does not meet the needs. Then in the process of test systems design, a new modeling and performance evaluation method based on the generalized coloured stochastic Petri net (GCSPN) is used in the article. For example in the design of the radar automatic test system, the system structure, test resources and test function are firstly analyzed, then the GCSPN model of the system is built. The model needs to be made simple and decomposed on the rules. Moreover the systems resource utilization and test time are evaluated on the stochastic Petri net. At last, the radar test system is built up referring to the Petri net model. The system runs normally, and the test values are almost consistent with the evaluations. It is compared with the parallel system designed by TestStand software. The result embodies the advantages of the GCSPN modeling method.

Analog Circuits Fault Diagnosis Based on Support Vector Machine

In this paper a new method for diagnosing analog circuits fault based support vector machine (SVM) is presented. The fault features are extracted from the frequency domain response of circuit under test (CUT) and the SVM which trained by the fault features is used to recognize and classify the unknown faults. Support vector machine is simple in architecture and strong generalization ability. The experimental results show that the proposed method for diagnosing analog circuits fault based on SVM correctly classifies faulty components with more than 99% accuracy.

Built-in Self-test Scheme for IIR Digital Filter

A built-in self-test (BIST) scheme is proposed for IIR digital filter chip. It needs no modification of the basic building cells and can detect all the non-redundant stuck-at faults in reasonable time. The testability of its cells is analyzed and the deterministic test sequence is deduced. By reusing available arithmetic function units such as adder to generate test vectors and compact test responses, this scheme can be implemented at-speed with minimum hardware overhead and performance degradation.

Research on speed regulation algorithm and fault detection of DC speed regulation system

This paper designs a speed-current dual close DC speed regulation system (SRS) and introduces the systems fault detection/protection strategy. The speed regulation (SR) algorithm is the core component of the SRS. By studying the SR principle and dynamic transfer function of SRS, adopting the flow of first interior last exterior loop, designs the SR algorithm. The algorithms Matlab simulation results and real systems running effect based on the algorithm are presented.

Product of Two Time-Frequency Representations

Each time-frequency representation (TFR) has both its own advantages and disadvantages for nonstationary signal analysis. In this paper, an algorithm, nominated as product method, is proposed, which gains one new TFR by the product of two TFRs and integrates their advantages for some applications, especially keeps Wigner distributions (WDs) auto-term concentration and reduces the crossterms. Potential applications to some TFRs are discussed, such as short time Fourier transform and its spectrogram, Margenau-Hill-spectrogram distribution and WD. Then some instances illustrate that this simple method is valid and practicable, and has much less computational complexity except for the initial TFRs and better visual effect in virtue of auto-term concentration enhancement and cross-term reduction.

Path Delay Fault Design For Test and Testability Analysis of Conditional Sum Adders

Conditional sum adders (CSA) are kinds of high-speed adders and the existing delay faults have crucial influence on their performance. Detail path delay fault testability analysis is proposed and a design-for-test scheme with low overhead and low size of test set is presented which can guarantee single path propagating hazard-free fully robust path delay fault testability of CSA. This is the strictest requirement for path delay fault testing. Based on the scheme, a test set of minimal size is derived by exploiting its structural property and parallel testing.

A Research on IDDT Test Pattern Generation Algorithm Based on Digragh Model

According to the CMOS NAND gate model, we present a transient current (IDDT) test pattern automatic generation algorithm based on digraph model in this paper. First, we describe the IDDT path that may be formed of a CMOS NAND gate when inputs change, and build the generation table. Next, we build all IDDT path digraph models by regarding the inputs which can generate IDDT as the IDDT test patterns. Based on it, we present a corresponding IDDT test vectors generation algorithm. The results of experiment demonstrate that this algorithm has good precision and efficiency.