Xie Yongle

Wavelet neural network based fault diagnosis in nonlinear analog circuits

Abstract The theories of diagnosing nonlinear analog circuits by means of the transient response testing are studied Wavelet analysis is made to extract the transient response signature of nonlinear circuits and compress the signature dada. The best wavelet function is selected based on the between-category total scatter of signature. The fault dictionary of nonlinear circuits is constructed based on improved back-propagation(BP) neural network Experimental results demonstrate that the method proposed has high diagnostic sensitivity and fast fault identification and deducibility.

Feature evaluation and extraction based on neural network in analog circuit fault diagnosis

Abstract Choosing the right characteristic parameter is the key to fault diagnosis in analog circuit. The feature evaluation and extraction methods based on neural network are presented. Parameter evaluation of circuit features is realized by training results from neural network; the superior nonlinear mapping capability is competent for extracting fault features which are normalized and compressed subsequently. The complex classification problem on fault pattern recognition in analog circuit is transferred into feature processing stage by feature extraction based on neural network effectively, which improves the diagnosis effciency. A fault diagnosis illustration validated this method.

Built-in Self-test Scheme for IIR Digital Filter

A built-in self-test (BIST) scheme is proposed for IIR digital filter chip. It needs no modification of the basic building cells and can detect all the non-redundant stuck-at faults in reasonable time. The testability of its cells is analyzed and the deterministic test sequence is deduced. By reusing available arithmetic function units such as adder to generate test vectors and compact test responses, this scheme can be implemented at-speed with minimum hardware overhead and performance degradation.

Path Delay Fault Design For Test and Testability Analysis of Conditional Sum Adders

Conditional sum adders (CSA) are kinds of high-speed adders and the existing delay faults have crucial influence on their performance. Detail path delay fault testability analysis is proposed and a design-for-test scheme with low overhead and low size of test set is presented which can guarantee single path propagating hazard-free fully robust path delay fault testability of CSA. This is the strictest requirement for path delay fault testing. Based on the scheme, a test set of minimal size is derived by exploiting its structural property and parallel testing.

Low overhead design-for-testability for scan-based delay fault testing

Abstract An efficient design-for-testability (DFT) technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. Whats more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.

Funcational Test with Single Compaction Output for Digital IP Cores

In this paper, a novel functional test methodology with single compaction output for embedded digital intellectual property cores on a system-on-a-chip is proposed. The functional test method is independent of the fault model and the structure of the core under test and uses only the knowledge of the test set and corresponding fault-free responses. In addition, advantages of our approach include single compaction output and implementation only by single test application. Hence, as test time consumption is concerned, the method excels those counterparts, in which single compaction output with zero-aliasing is obtained via two step or two mode. Also, in order to lower hardware overhead, encoding technique is adopted to both normal response and practical response during test application, so we improved the idea to deal with similar problem