Chen Tianzhou

The Android Application Development College Challenge

Since mobile devices have become more and more powerful and distributive, mobile computing has greatly changed our daily life. As one of the most popular mobile operating systems, Android provides the tools and API for Android developer to develop Android applications. The Android application development college challenge is a influential Android developer contest for college students in China. This contest has been held for two times since 2010. It encourages college students to design and implement their applications on the Android platform. In this way, it gives the students an opportunity to show their creativity and learn about the development of Android applications. The influence of the contest is keeping increasing, and students from more universities and regions take part in the contest. In this paper we introduce the organization of such a contest.

A Practical Dynamic Frequency Scaling Scheduling Algorithm for General Purpose Embedded Operating System

Dynamic frequency scaling (DFS) techniques for real-time embedded systems have been widely studied. However, most of the scheduling algorithms so far concern only special purpose real-time systems. In this paper we devise a power-aware parameter task model for time-sharing real-time systems of general purpose, as well as a scheduling algorithm that is based on the task model. We implement the model and corresponding algorithm on embedded Linux. With the energy consumption measurement method presented in this paper, the experiment shows that for real-time tasks in Linux, 31.7% power consumption can be saved compared with the circumstance under which the processor runs at highest frequency.

Dynamic power management framework for multi-core portable embedded system

In this paper we introduce dynamic power management framework for multi-core embedded system. This is a novel architecture for multi-core embedded system. In this framework user can add user defined policies to the architecture. And user also can add some running constrains to the framework. This framework could parse the user input, and give the right power control instruction to the global policy layer.In this paper we introduce dynamic power management framework for multi-core embedded system. This is a novel architecture for multi-core embedded system. In this framework user can add user defined policies to the architecture. And user also can add some running constrains to the framework. This framework could parse the user input, and give the right power control instruction to the global policy layer.

A fast algorithm for energy-aware mapping of cores onto WK-recursive NoC under performance constraints

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. Mapping an application, which is described by a parameterized task graph, onto NoC is a key research problem in NoC design. In this paper, we first propose an energy-aware cores mapping approach on WK-recursive NoC, and then present a fast clustering-based scheduling algorithm that maps the cores onto WK-recursive NoC architecture under bandwidth constraints to minimize the total communication energy. Experimental results show that the proposed algorithm is able to handle large task graphs and provide near optimal cores mapping in a few seconds on a PC platform.

A real-time scheduling algorithm for embedded systems with various resource requirements

The scheduling algorithm is one of the most important portions of embedded operating systems especially for real-time embedded operating systems. The performance of scheduling algorithm influences the performance of the whole system. Real-time embedded operating system needs better response time for real-time process; it is more rigid on response time for hard real-time embedded operating system. A high-performance scheduling algorithm is required in order to make embedded operating system more efficient. Most of the mainstream scheduling algorithms are able to ensure response time for most processes, but for specific real-time applications for embedded system, a specialized real-time scheduling algorithm is required to ensure real-time response. In this paper, we propose a novel real-time scheduling algorithm for real-time embedded system. This algorithm divides all tasks into different sets and schedules the tasks according to the features of the set

Distributed Memory Management Units Architecture for NoC-based CMPs

Network on Chip (NoC) is considered as the promising diagram of interconnection mechanism for future chip multiprocessors. As the number of processing elements (PE) on chip keeps growing, the delay for simultaneous memory references of these PEs is emerging as a serious bottleneck on high performance. One major part of this delay is from the Memory Management Unit (MMU) due to its centralized structure. In this paper, we propose a novel distributed MMU architecture for NoC-based CMPs, which can effectively reduce the bottleneck effect in contrast of traditional MMU. We discuss the benefit of this architecture in aspects of TLB hit rate, network communication efficiency, memory bandwidth and coherence. Experimental results show that the distributed MMU structure significantly improves network throughput balance and lowers communicational delay.

Balance the battery life and real-time issues for portable real-time embedded system by applying DVS with battery model

Power consumption and real-time have been two of the major constraints in the mobile computing system design. Much work has been done to study the relationship between power, performance and real time issues. Many of existing studies assumed that the energy of the battery is a constant parameter. In fact, the energy of the battery is affected by the load current. This paper presents a battery model driven power aware real-time software system design. In this paper we take the characteristics of battery into account. And our work is applying DVS to hard real time embedded system with battery model. This new approach is more accurate to reflect the tradeoff between battery life and real-time performance.

Model Curriculum Construction of Embedded System in Zhejiang University

Embedded systems have been used widely promoted by the advancement of semiconductor technology. This also makes embedded system education a challenge for the universities. The curriculum in embedded system should address the needs from embedded systems and embedded software. In this paper, we shared our experiences in embedded system education and the model curriculum construction of embedded system in Zhejiang University.

Design and Analyze the Communication in the Multi-Core Soc Driven by Petri Net

With the development of integrated circuit, SoC technology has played an important role gradually. To increase the speed of the chip and system design further, multi-core architecture has been a new trend in the SoC field, while an important problem of multi- core architecture is the communication among the different cores. In this paper, Petri net is used as a model to describe asynchronous and concurrent computer system, including strict mathematics definition, audiovisual figure show, abundant of describing methods and analysis technology. A formal co-verification approach of SoC with controlled Petri net tools is proposed and an example is described in detail, including the abstract of the design and the analysis of the multi-core SoC system from the definition of Petri net to the use of these tools.

An Agile BSP Modeling Methodology: Cross Platform BSP Framework (CPBF)

An agile modeling methodology for building BSP called cross platform BSP framework (CPBF) is introduced in this paper. We propose an operating system independent unified cross platform BSP architecture; setup a BSP framework which mainstream embedded operating systems like Linux, WinCE, PalmOS and Symbian can build on. CPBF consists of two parts, they target at boot loader initialization and device drivers respectively. The design methodology and guidelines are discussed in detail, and then illustrated by practical audio codec design on Intel XScale development board for example. This framework can accelerate the BSP development and simplify the maintenance work of a specified processor or SOC platform remarkably