Shi Qingsong

Dynamic power management framework for multi-core portable embedded system

In this paper we introduce dynamic power management framework for multi-core embedded system. This is a novel architecture for multi-core embedded system. In this framework user can add user defined policies to the architecture. And user also can add some running constrains to the framework. This framework could parse the user input, and give the right power control instruction to the global policy layer.In this paper we introduce dynamic power management framework for multi-core embedded system. This is a novel architecture for multi-core embedded system. In this framework user can add user defined policies to the architecture. And user also can add some running constrains to the framework. This framework could parse the user input, and give the right power control instruction to the global policy layer.

Distributed Memory Management Units Architecture for NoC-based CMPs

Network on Chip (NoC) is considered as the promising diagram of interconnection mechanism for future chip multiprocessors. As the number of processing elements (PE) on chip keeps growing, the delay for simultaneous memory references of these PEs is emerging as a serious bottleneck on high performance. One major part of this delay is from the Memory Management Unit (MMU) due to its centralized structure. In this paper, we propose a novel distributed MMU architecture for NoC-based CMPs, which can effectively reduce the bottleneck effect in contrast of traditional MMU. We discuss the benefit of this architecture in aspects of TLB hit rate, network communication efficiency, memory bandwidth and coherence. Experimental results show that the distributed MMU structure significantly improves network throughput balance and lowers communicational delay.

Model Curriculum Construction of Embedded System in Zhejiang University

Embedded systems have been used widely promoted by the advancement of semiconductor technology. This also makes embedded system education a challenge for the universities. The curriculum in embedded system should address the needs from embedded systems and embedded software. In this paper, we shared our experiences in embedded system education and the model curriculum construction of embedded system in Zhejiang University.

Dual OS Support Peripheral Device Encapsulation

The need of extensive computing capacity is expanding all the time. Especially in company providing network service, adding servers physically requires much more cost. Also in embedded system, resource is also very limited. That is why virtulization is so popular in research and industry application. A lot of virtulization technique is raised to supply great computing capacity with multiple operating system running synchronously in a single real machine. Of all the aspects affecting real time performance of a computer, I/O processing has played a major role. Because I/O bound process has to wait for device to be free and thus increase response time which may delay them go beyond deadline. The system-on-a-chip technology provides the scratch-pad memory(SPM), which is small, isolated and located on chip. We implement a little operating system running in SPM (SPMOS). The SPMOS provide virtual I/O interface for general operating system. Different I/O requestis buffered and scheduled if necessary. Also, with proper memory checking mechanism, we could prevent malicious attacks on SPM, which means that any program running in the SPM could be protected effectively. Experiment shows that the SPMOS based virtual I/O interface is efficient and practical.

Component-based Network Protocol Architecture for Multi-core

The architecture and implementation of network protocol stack is very important for network communication. And now CMP(Chip Multi-processor) architecture is the trend of CPU because of its excellent parallelism and high efficiency. So this paper proposes a Component-based Network Protocol Architecture(CNPAM) based on Intel Multi-core. In this architecture, two important modules are brought in: distribution module and migration module. Distribution module takes charge of distributing close function components to the same core group in which the two cores share the L2 cache. And migration module guarantees the load balance of all cores. The performance of CNPAM gets a significant improvement.

SPMOS-Based Intrusion Detection Architecture

Security of embedded systems is becoming more and more important. IDS (instrusion detection system) has been designed to protect systems from being compromised by network attacks. A lot of researches have been done on it. However, most of them focus on complex and time-consuming detection methods to improve accuracy of the system, with assumption that IDS is running under control of general purpose operating systems (GPOS). In this way, the IDS itself will depress overall performance and cannot be guaranteed secure. In this paper, we present an embedded architecture of SPMOS-based IDS. SPMOS, located in SPM, is a little OS running under GPOS. Experiment results show that the architecture is fast. Based on this, we also design a simple IDS and conduct tests by integrating it into SPMOS and GPOS. The former consumes the latters 8.3% time only, with less than 6.2% overhead, which verifies the architecture proposed is practical and efficient.

Power-Aware Code Restructuring for Embedded Parallel Storing Device

In order to cope with the energy challenge emerging with the process of parallelism in embedded storing device, this paper focuses on the static code restructuring of nested loop array accessing related to storing device. Departing the running time of different devices can extend the duration time when it is in low- power state. Experiment shows that power-aware code restructuring can effectively reduce state switching times and extra power wasted. Static method described in this paper can achieve up to 12% power reduction if it cooperates with proper dynamic method.

PZSPTF: Parallelism-aware and Zone-based Shortest Positioning TimeFirst Scheduling for MEMS-based Storage Devices

MEMS-based storage device is a new candidate of storage device for pervasive applications which requires large volume of storage. Because of its attractive features such as high-bandwidth, low-power consumption, and low cost compared with hard disk, the storage performance could be significantly improved by adopting MEMS-based storage devices, especially when employing new request scheduling algorithm and data placement A new request scheduling algorithm is explored for MEMS-based storage devices in this paper, which is named parallelism-aware and zone-based shortest positioning time first (PZSPTF). And a new data placement scheme is also introduced, with which the storage area is divided into 2 parts according to 2 file classes, and the files of same class will be stored in the same part. Experiments show that the new PZSPTF algorithm improves the performance of MEMS storage by 7.83% to 18.51% compared with the widely acknowledged request scheduling algorithm FCFS (first-come, first-served).

Online Programming Experience Platform for Multicore Curriculum

Multicore has shown its merits of high performance and low power consumption compared with traditional single cores. It also puts a challenge to the universities in how to teach and train the students in this rapidly changing field. In this paper we present the online programming experience platform designed and implemented for multicore curriculum. Teaching effect indicates that this platform is beneficial for multi-core programming.