Chen-Yen Ho

A 64-fJ/Conv.-Step Continuous-Time

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.

\Sigma \Delta

This paper presents a power-efficient single-loop continuous-time (CT) ΔΣ modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm 2.

Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital

A high-dynamic-range (DR) CT ΔΣ modulator is required to relax the analog front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [1], a CT ΔΣ modulator embedded with a 2nd-order active filter and VGA is reported to extend the DR. However, the additional active filter results in a complicated architecture as well as extra area that is not preferred in advanced processes. An alternative method that improves the DR is to adopt the self-coupled noise-injection technique introduced in [2] to increase by one the order of the noise transfer function (NTF). Unfortunately, it requires an accurate clock cycle delay, which is only available in the DT ΔΣ modulator. Apart from DR considerations, power efficiency is still limited by the building block design. Conventional excess loop delay (ELD) compensation [1,3,4] is implemented by an inner DAC, which increases the power consumption and loads the last integrator with a large parasitic capacitance, especially for a multi-bit modulator. Therefore, a high-bandwidth opamp is required in the last integrator to alleviate the phase delay of the loop filter. Furthermore, to address the nonlinearity of a multi-bit DAC, 2nd-order dynamic element matching (DEM) is used in [5] to reduce data-dependent switching. The SFDR is still limited to 90dB. In this paper, CT self-coupling (CTSC), residual ELD compensation, and DAC linearity enhancement techniques are introduced to overcome these challenges. Our CT ΔΣ modulator achieves an SNDR of 90.4dB with an FoMs (SNDR) of 177.3dB in a 2.2MHz bandwidth.

\Delta \Sigma

This paper presents a high linear analog front-end (AFE) for ADSL/ADSL2+ system applications. This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops. The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency. The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost. Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption. The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.

Truncator

A 3rd-order single-loop continuous time sigma-delta modulator (CTSDM) with 6-bit asynchronous SAR quantizer and digital delta-sigma truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed asynchronous SAR based quantizer reduces the area and power dramatically with the help of digital truncation technique. In addition, the modulator incorporating the proposed operational amplifiers (op-amp) with ac coupled push-pull stage is to improve the high frequency driving capability. The modulator sampling at 65MHz achieves 83.4dB dynamic range (DR) and 80/79.6dB peak SNR/SNDR with 1.92MHz bandwidth (BW) in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Implemented in 40nm CMOS, the modulator occupies 0.051mm2 and consumes 1.91mW from a 1.2V supply. A 64fJ/conversion figure of merit (FOM) is achieved.

A 4.5 mW CT Self-Coupled

A 4th-order resistive feed-forward continuous time sigma-delta modulator (CTSDM) for a worldwide analog/digital TV-receiver is presented. The proposed hybrid integrator of the modulator is developed in order to save the summing amplifier and reduce total area. In addition, the modulator incorporates the proposed low power operational amplifiers (op-amp) with active feed-forward compensation to reduce power consumption in the loop filter. The prototype chip is implemented in a 55nm CMOS process which occupies 0.132 mm2. Measurements show that the proposed modulator achieves 80.2dB dynamic range, 75.1dB SNDR, and an effective number of bits (ENOB) of 12.2 bits over 5 MHz signal bandwidth. The figure of merit (FOM) is 0.28 pJ/conversion at 1.3 V supply.