Hung-Chieh Tsai

A 64-fJ/Conv.-Step Continuous-Time

A third-order single-loop continuous-time sigma-delta modulator (CTSDM) with 6-bit asynchronous successive approximation register (ASAR) quantizer and digital ΔΣ truncator for WCDMA/GSM/EDGE cellular systems is presented. The proposed ASAR-based quantizer reduces the area and power of the modulator dramatically by utilizing the digital truncation technique. By using the 6-bit ASAR quantizer, the sampling frequency is lowered, which reduces the design efforts not only in system level but also in the modulator. In addition, the ac-coupled push-pull stage is employed to improve the high-frequency driving capability of the first integrator. Sampling at 65 MHz, the modulator achieves 83.4 dB dynamic range (DR) and 80/79.6 dB peak SNR/SNDR with 1.92 MHz bandwidth in WCDMA mode. In GSM/EDGE mode, the DR is 96.2 dB. Fabricated in 40-nm CMOS, the modulator occupies 0.051 mm 2 and consumes 1.91 mW from a 1.2-V supply. A 64fJ/conv.-step figure of merit is achieved.

\Sigma \Delta

This paper presents a power-efficient single-loop continuous-time (CT) ΔΣ modulator (DSM) that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a fourth-order feed-forward architecture incorporating the continuous-time self-coupling (CTSC) technique. Moreover, to reduce hardware area, this design utilizes the residual signal for excess loop delay (ELD) compensation. To improve linearity, low-ripple DAC latches and low toggle-rate dynamic element matching (DEM) algorithm are adopted. This DSM is fabricated in a 55 nm LP CMOS technology. Operating at 140 MHz sampling rate, the chip consumes 4.5 mW from power supplies of 1.2 V and 1.8 V. It achieves 90.4 dB SNDR and 92 dB dynamic range (DR) with a 2.2 MHz signal bandwidth, resulting in a Schreier FOM of 177.3 dB and 178.9 dB based on SNDR and DR, respectively. The chip area is 0.09 mm 2.

Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital

In this paper, we present a low-power high-performance WiMAX chipset fully compliant with IEEE 802.16e specification corrigendum 1, 2 for mobile broadband access and WiMAX Forum system profile Wave2. The chipset is comprised of a 632.7-mW/24.99-mm2 modem/router chip and a 364-mW/11.05- mm2 dual-band 2 × 2 MIMO RF transceiver chip, both developed in 65-nm CMOS process. The proposed chipset is capable of handling a maximum peak WiMAX downlink (DL) throughput of 70 Mbps. Moreover, the chipset can reach up to -100.5-dBm sensitivity in a 10-MHz AWGN channel, which outperforms WiMAX Forum mobile radio conformance test (MRCT) by 9.5 dB. Such high sensitivity is due to the proposed low-noise high-linearity RF transceiver chip, which has 2.5-dB RX noise figure (NF) and -37-dB TX error vector magnitude (EVM), and the applied high-performance baseband signal processing algorithms. Several low-power design techniques-from SW level, firmware/DSP level, to HW module level-have been implemented to enable portable applications. The modem/router chip is highly integrated and has rich features and various interfaces for applications such as router or VoIP phone. Furthermore, this is the only published WiMAX chipset which has been in mass production.

\Delta \Sigma

A high-dynamic-range (DR) CT ΔΣ modulator is required to relax the analog front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [1], a CT ΔΣ modulator embedded with a 2nd-order active filter and VGA is reported to extend the DR. However, the additional active filter results in a complicated architecture as well as extra area that is not preferred in advanced processes. An alternative method that improves the DR is to adopt the self-coupled noise-injection technique introduced in [2] to increase by one the order of the noise transfer function (NTF). Unfortunately, it requires an accurate clock cycle delay, which is only available in the DT ΔΣ modulator. Apart from DR considerations, power efficiency is still limited by the building block design. Conventional excess loop delay (ELD) compensation [1,3,4] is implemented by an inner DAC, which increases the power consumption and loads the last integrator with a large parasitic capacitance, especially for a multi-bit modulator. Therefore, a high-bandwidth opamp is required in the last integrator to alleviate the phase delay of the loop filter. Furthermore, to address the nonlinearity of a multi-bit DAC, 2nd-order dynamic element matching (DEM) is used in [5] to reduce data-dependent switching. The SFDR is still limited to 90dB. In this paper, CT self-coupling (CTSC), residual ELD compensation, and DAC linearity enhancement techniques are introduced to overcome these challenges. Our CT ΔΣ modulator achieves an SNDR of 90.4dB with an FoMs (SNDR) of 177.3dB in a 2.2MHz bandwidth.