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Featured researches published by Cheng Hsiao.


custom integrated circuits conference | 2013

Circuit reliability simulation using TMI2

Min-Chie Jeng; Cheng Hsiao; Ke-Wei Su; Chung-Kai Lin

Using simulation to assess the impacts of various reliability mechanisms to circuit performance has become prevail for advanced technologies due to smaller headroom (=Vdd-Vth) and less design margins. This paper reviews existing circuit aging simulation approaches with focus on TMI. The limitations of aging models are also discussed so that reliability simulations can be executed more correctly with the right expectation. An example circuit under multi-waveform and multi-temperature stress is presented to illustrate reliability simulation flow through TMI.


international conference on simulation of semiconductor processes and devices | 2011

A smart approach for process variation correlation modeling

Chung-Kai Lin; Cheng Hsiao; Wei-Min Chan; Min-Chie Jeng

Process variation has become a serious concern in nanometer technologies. Designs with competitive margins rely on well-characterized statistical models, which must predict the magnitude and scalability of variability accurately. In this paper, we propose a novel approach in creating the statistical models, which tracks the global variation correlation among logic and SRAM devices, hence more realistic. The simulation result is verified with TSMC N28 technology silicon. Two types of circuits, SRAM Vccmin calibration and a SRAM tracking circuit with logic, are discussed in this paper. Different simulation setups are applied on these two circuits to understand the impact of device correlation for the SRAM performance and design margin setting.


international conference on simulation of semiconductor processes and devices | 2014

Unifying self-heating and aging simulations with TMI2

Wai-Kit Lee; Kasa Huang; Jim Liang; Juan-Yi Chen; Cheng Hsiao; Ke-Wei Su; Chung-Kai Lin; Min-Chie Jeng

In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI approach for self heating simulations takes much shorter simulation time.


international conference on simulation of semiconductor processes and devices | 2017

A unified aging model with recovery effect and its impact on circuit design

Wai-Kit Lee; Kasa Huang; Li Chung Hsu; Clement Huang; Jim Liang; Julian Chen; Cheng Hsiao; Ke-Wei Su; Chung-Kai Lin; Min-Chie Jeng

In this paper we not only discuss how to implement the recovery effect with TMI but also give various examples to show that without considering the recovery effect, the design margin of a system can be either under- or over-estimated. To validate our modeling methodology, the simulation results are benchmarked with measurement data.


international conference on simulation of semiconductor processes and devices | 2016

A comprehensive solution for BEOL variation characterization and modeling

Katherine H. Chiang; Jun-Fu Huang; Tai-Yu Cheng; Cheng Hsiao; Joshua Sun; Chun Cheng; Kuo-Pei Lu; Ke-Wei Su; Chung-Kai Lin; Kevin Chen; King-Ho Tam; Te-Yu Liu; Ke-Ying Su; Min-Chie Jeng

A comprehensive variation model is critical to achieve both competitive design and manufacturing yield in advanced technologies. Conventionally, as long as FEOL (front end of line) statistical model is appropriate, BEOL (back end of line) variations given by lumping multiple variation sources into few corners is enough to achieve reliable simulation results. However, as BEOL contribution is becoming more important with device scaling, simulation results with conventional corner model may not always produce optimal design margin. We thus propose a more comprehensive solution for BEOL variations characterization and modeling associated with statistical Monte Carlo simulation.


Archive | 2010

Constructing Mapping Between Model Parameters and Electrical Parameters

Chen-Ming Tsai; Ke-Wei Su; Cheng Hsiao; Min-Chie Jeng; Jia-Lin Lo; Feng-Ling Hsiao; Yi-Shun Huang


Archive | 2010

Circuit device reliability simulation system

Jia-Lin Lo; Ke-Wei Su; Min-Chie Jeng; Feng-Ling Hsiao; Cheng Hsiao; Yi-Shun Huang; Yi-Chun Chen


Archive | 2011

Accelerated Generation of Circuit Parameter Distribution Using Monte Carlo Simulation

Cheng Hsiao; Ke-Wei Su; Chung-Kai Lin; Min-Chie Jeng


Archive | 2017

METHOD FOR ANALYZING INTERCONNECT PROCESS VARIATION

Te-Yu Liu; Cheng Hsiao; Chia-yi Chen; Wen-cheng Huang; Ke-Wei Su; Ke-Ying Su; Ping-hung Yuh


Archive | 2014

Simulation Scheme Including Self Heating Effect

Min-Chie Jeng; Chung-Kai Lin; Ke-Wei Su; Yi-Shun Huang; Ya-Chin Liang; Cheng Hsiao; Juan Yi Chen; Wai-Kit Lee

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