Ke-Wei Su

A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics

This paper demonstrates a new compact and scaleable model of mechanical stress effects on MOS electrical performance, induced by shallow trench isolation (STI). This model has included the influence of STI stress not only on the mobility and saturation velocity, but also on the threshold voltage and other important second-order effects. Thus it could simulate the layout dependence of MOS performance with good accuracy and efficiency. We have verified this model with various device dimensions and layout styles of our advanced MOS technologies. And it shows the importance of this new model for circuit design in advanced CMOS generations.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Modeling well edge proximity effect on highly-scaled MOSFETs

Well edge proximity effect caused by ion scattering during implantation in highly-scaled CMOS technology was explored from a process and physics point of view. TCAD simulation was employed to visualize the internal change of the MOSFETs. A new compact model for SPICE was proposed using physics-based understanding and was calibrated with experimental silicon test sets. Circuit simulation using the proposed model was conducted to evaluate the improvement in accuracy

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.

Modeling isolation-induced mechanical stress effect on SOI MOS devices

In this paper, the mechanical stress effect of SOI MOS devices was analysed. The width dependence of stress effect and drain current shift were evaluated.

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 mum, the inner-sidewall-oxide fringing capacitance (CFIS), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at VG=0.3 V and VD=1 V, is the second largest contributor to the gate-source capacitance (C GS). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 mum, CFIS cannot be overlooked for modeling gate-source/drain capacitance (CGS/CGD)

Investigation of Anomalous Inversion C – V Characteristics for Long-Channel MOSFETs With Leaky Dielectrics: Mechanisms and Reconstruction

This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (Rii). The concept of Rii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (~95% for L = 20 mum) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed Rii approach may provide an option for regular process monitoring purposes.

Inversion MOS capacitance extraction for ultra-thin gate oxide using BSIM4

In this work, we investigate the distorted C-V characteristics for MOSFETs with ultra-thin gate oxide. We propose a scalable BSIM4-based macro model to simulate the anomalous C-V behavior. Based on the model, we develop a methodology to extract the true MOS capacitance.

An Assessment of Single-Electron Effects in Multiple-Gate SOI MOSFETs with 1.6-nm Gate Oxide near Room Temperature

To allow high-temperature operation, the size of the SET needs to be further reduced (Peters et al., 1998). The suppression of short-channel effects, therefore, is especially critical to enabling single-electron tunneling at elevated temperature in the scaled MOSFET. In this work, we control the short-channel effect for devices with gate length down to 30 nm using thin oxide and multiple-gate SOI structures. We conduct an assessment of single-electron effects in our multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature