Cheng-Hsiao Lai

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction

A novel logarithmic response 0.25 /spl mu/m CMOS image sensor technology for high output swing and low noise error is proposed. The experimental results show that the new cell has 4 times higher output voltage swing. Optimized simulation results show 6.5 times larger output voltage swing, which is achievable for an input signal range of 0.01 lux to 100,000 lux. With this wider swing, the effect of fixed pattern noise (FPN) reflecting on the digital output can be reduced significantly. In addition, after adding a correlated double sampling (CDS) control transistor, the output voltage difference variation due to FPN is greatly reduced from 73 mV to 15 mV.

A 1.2-V 0.25-/spl mu/m clock output pixel architecture with wide dynamic range and self-offset cancellation

A 10T/pixel CMOS digital pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. The pixel fabricated by a standard 0.25-/spl mu/m CMOS logic process comprises a reset transistor, a photo-diode, a comparator, and an inverter with pixel size of 9.4/spl times/9.4 /spl mu/m/sup 2/ and 24% fill factor. The amplified logarithmic output response similar to the light response of human eye is demonstrated in this work. The pixel can operate at a supply voltage as low as 1.2 V without affecting its output characteristics. The dynamic range of this cell limited by either the subsequent analog-to-digital circuit resolution or the rising and falling time of output clock is higher than 90 dB with an 8-bit resolution.

A four transistor CMOS active pixel sensor with high dynamic range operation

A new CMOS APS using standard CMOS logic technology is proposed to allow high dynamic range operation. The new cell is constructed by incorporating one additional transistor to the conventional three transistor APS. The experimental results demonstrate that extended dynamic range is obtained when operates with a ramped reference voltage source. The cell offers flexible nonlinear transfer characteristics, which can be designed by modifying the operational timing diagram. Furthermore, charge collection on the parasitic capacitor allows for the use of the signal due to hole accumulation. An alternative operation of this cell is also proposed to provide enhanced characteristics in both its sensitivity and dynamic range.

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

A high fill-factor self-buffered active pixel sensor and a tunable injection current compensation architecture for high dynamic range imager is proposed for scaled CMOS technology. The new cell, including a photodiode, is formed by n-well and p-type substrate and a single-transistor output buffer can achieve fill-factor of 55%. Dynamic range of up to 120 dB is projected by simulation results. Experimental results for the new structure and simulated design of the circuit are discussed in this work.

A logarithmic response complementary metal oxide semiconductor image sensor with parasitic P-N-P bipolar junction transistor

Logarithmic-response complementary metal oxide semiconductor (CMOS) active pixel sensors provide a desirable attribute of wide dynamic range even with low supply voltages. In this paper, a log-mode pixel with employing parasitic P–N–P bipolar junction transistor (BJT) to amplify photo-current is investigated and optimized. A new log-mode cell with a calibration transistor is proposed to increase the output voltage swing as well as to reduce the fixed pattern noise. The measurement results demonstrate that, the output voltage swing of this new cell is enhanced by 4× and fixed pattern noise (FPN) of a pixel array can be reduced by 10× comparing to that of a conventional log-mode CMOS active pixel sensor.

A 1.2V 0.25-μm clock output pixel sensor with wide dynamic range

A 10T/pixel CMOS active pixel sensor with clock count output, ultra low supply voltage, and wide dynamic range is presented. This pixel comprises a reset transistor, photo-diode, a comparator, and an inverter with pixel size of 9.4x9.4μm2 and 24% fill factor in a standard 0.25-μm CMOS logic technology. The output transfer curve is the same as an amplified logarithmic-response and is similar to the light response of the human eye. Besides, the pixel can operate at an ultra low supply voltage and the output characteristics will not be affected. Even with supply voltage down to 1.2V, the dynamic range of this pixel can remain as high as 90dB.

A new well capacity adjusting scheme for high sensitivity, extended dynamic range CMOS imaging pixel sensors

An embedded 3T active-pixel complementary metal oxide semiconductor (CMOS) image sensor, fabricated with a standard 0.25-µm CMOS logic process with new well capacity adjusting scheme is proposed to extend dynamic range. The photo-sensing device consists of a photo-gate area and a photo-diode, and the well capacity is adjusted by controlling the pulse voltage on the photo-gate. Besides, the imaging sensitivity can be improved through optimizing the photo-gate to photo-diode area ratio and the pulse high level of photo-gate voltage. The experimental results demonstrate that the pixel can achieve both high sensitivity at low illumination and extended dynamic range of 25 dB under high illumination.

Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Cell Using n+ Ring Reset

An ultra low dark current pixel has been developed for embedded active-pixel complementary metal oxide semiconductor (CMOS) image sensors using a standard CMOS logic process. Conventional CMOS image sensors suffer from high dark current as a result of the high interface state density at the field oxide edge. In the proposed novel pixel, the photo-sensing diode is surrounded by a ring-shaped poly-silicon reset gate which isolates the photo-sensing area from the field oxide edge. Hence, the dark current level can be effectively reduced. However, in the novel pixel, the large overlap capacitance between the reset poly-gate ring and the sensing node can severely affect the output swing. To optimize this novel pixel, the poly-silicon gate is limited to isolate the photo-sensing area from the field oxide edge. Furthermore, a constant bias voltage applied to the poly-silicon gate provides an additional advantage of extended dynamic range. The effects of technology scaling on the pixel performance are investigated as well.

A New Sampling Scheme for High-Sensitivity, Extended-Dynamic-Range Complementary Metal Oxide Semiconductor (CMOS) Imaging Pixel Sensors

A new sampling scheme for extending the dynamic range of a high-sensitivity complementary metal oxide semiconductor (CMOS) image sensor is proposed. The photodiode-type CMOS pixel imager, consisting of a transfer gate transistor for transporting photoelectrons from a sensing region to a readout region, is highly sensitive but suffers form a poor dynamic range. The new sampling scheme and a ratiometric processing circuit can improve the dynamic range of the pixel imager by about 24 dB by making use of the photo response of the readout node. Optimization of the sensing region area/readout region area can be applied to specific applications such as low-light imaging and high-speed imaging applications. Experimental results indicate that this pixel can maintain high sensitivity at low illumination while obtaining an extended dynamic range about 10 dB higher than that of the conventional 3-transistor (3-T) photodiode-type CMOS pixel imager.