Shi-Yu Huang

Formal Equivalence Checking and Design DeBugging

Foreword. Preface. 1. Introduction. Part I: Equivalence Checking. 2. Symbolic Verification. 3. Incremental Verification for Combinational Circuits. 4. Incremental Verification for Sequential Circuits. 5. AQUILA: A Local BDD-Based Equivalence Verifier. 6. Algorithm for Verifying Retimed Circuits. 7. RTL-to-Gate Verification. Part II: Logic Debugging. 8. Introduction to Logic Debugging. 9. ErrorTracer: Error Diagnosis by Fault Simulation. 10. Extension to Sequential Error Diagnosis. 11. Incremental Logic Rectification. Bibliography. Index.

High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction

Feature extraction is an essential part in applications that require computer vision to recognize objects in an image processed. To extract the features robustly, feature extraction algorithms are often very demanding in computation so that the performance achieved by pure software is far from real-time. Among those feature extraction algorithms, scale-invariant feature transform (SIFT) has gained a lot of popularity recently. In this paper, we propose an all-hardware SIFT accelerator-the fastest of its kind to our knowledge. It consists of two interactive hardware components, one for key point identification, and the other for feature descriptor generation. We successfully developed a segment buffer scheme that could not only feed data to the computing modules in a data-streaming manner, but also reduce about 50% memory requirement than a previous work. With a parallel architecture incorporating a three-stage pipeline, the processing time of the key point identification is only 3.4 ms for one video graphics array (VGA) image. Taking also into account the feature descriptor generation part, the overall SIFT processing time for a VGA image can be kept within 33 ms (to support real-time operation) when the number of feature points to be extracted is fewer than 890.

Fault emulation: A new methodology for fault grading

In this paper, we introduce a method that uses the field programmable gate array (FPGA)-based emulation system for fault grading. The real-time simulation capability of a hardware emulator could significantly improve the performance of fault grading, which is one of the most time consuming tasks in the circuit design and test process. We employ a serial fault emulation algorithm enhanced by two speed-up techniques. First, a set of independent faults can be injected and emulated at the same time. Second, multiple dependent faults can be simultaneously injected within a single FPGA-configuration by adding extra circuitry. Because the reconfiguration time of mapping the numerous faulty circuits into the FPGAs is pure overhead and could be the bottleneck of the entire process, using extra circuitry for injecting a large number of faults can reduce the number of FPGA-reconfigurations and, thus, improving the performance significantly. In addition, we address the issue of handling potentially detected faults in this hardware emulation environment by using the dual-railed logic. The performance estimation shows that this approach could be several orders of magnitude faster than the existing software approaches for large sequential designs.

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.

Performance Characterization of TSV in 3D IC via Sensitivity Analysis

In this paper, we propose a method that can characterize the propagation delays across the Through Silicon Vias (TSVs) in a 3D IC. We adopt the concept of the oscillation test, in which two TSVs are connected with some peripheral circuit to form an oscillation ring. Upon this foundation, we propose a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in the oscillation ring – a distilling process. In this process, we perturb the strength of the two TSV drivers, and then measure their effects in terms of the change of the oscillation ring’s period. By some following analysis, the propagation delay of each TSV can be revealed. Monte-Carlo analysis of a typical TSV with 30% process variation on transistors shows that the characterization error of this method is only 2.1% with the standard deviation of 8.1%.

Quick scan chain diagnosis using signal profiling

In this paper we address the scan chain diagnosis problem. We propose a new diagnosis flow based on the concept of signal profiling to accurately pinpoint the location of a faulty flip-flop in a scan chain. As compared to the conventional cause-effect or effect-cause analysis, this approach is much more computationally efficient because it does not have to simulate the behaviors of a large number of fault candidates. Also, it is general and applicable to all kinds of faults because it does not assume any specific fault model. Experimental results indicate that this approach can instantly catch a fault within a scan chain quite accurately in most cases.

ErrorTracer: a fault simulation-based approach to design error diagnosis

This paper addresses the problem of locating error sources in an erroneous combinational circuit. We use a fault simulation-based technique to approximate each signals correcting power. The correcting power of a particular signal is measured in terms of the signals correctable set, namely, the maximum set of erroneous input vectors that can be corrected by re-synthesizing the signal. Only the signals that can correct every erroneous input vector are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Secondly, it delivers more accurate results than other simulation-based approaches because it is based on a more stringent condition for identifying potential error sources. Thirdly, it can be easily generalized to identify multiple errors. Experimental results on diagnosing circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach.

On improving the accuracy of multiple defect diagnosis

Logic defect diagnosis locates the defect spots in a digital IC that fail testing. It is one of the critical steps during the process of manufacturing yield improvement. Automatic defect diagnosis techniques for circuits with single defects have been improved significantly. However, the techniques for multiple defect diagnosis are still inadequate. In this paper, we propose an effective heuristic for diagnosing a full-scan design with multiple defects. Concepts called curable vectors and curable outputs are incorporated. By combining these two measures as a grading criterion, each signals possibility of being one of the defect spots is calculated with a high accuracy. Experimental results on ISCAS85 benchmark circuits indicate that the proposed method indeed outperforms the conventional heuristics.

ErrorTracer: design error diagnosis based on fault simulation techniques

This paper addresses the problem of locating error sources in an erroneous combinational or sequential circuit. We use a fault simulation-based technique to approximate each internal signals correcting power. The correcting power of a particular signal is measured in terms of the signals correctable set, namely, the maximum set of erroneous input vectors or sequences that can be corrected by resynthesizing the signal. Only the signals that can correct every given erroneous input vector or sequence are considered as a potential error source. Our algorithm offers three major advantages over existing methods. First, unlike symbolic approaches, it is applicable for large circuits. Second, it delivers more accurate results than other simulation-based approaches because it is based on a more stringent condition for identifying potential error sources. Third, it can be generalized to identify multiple errors theoretically. Experimental results on diagnosing combinational and sequential circuits with one and two random errors are presented to show the effectiveness and efficiency of this new approach.

AQUILA: An equivalence verifier for large sequential circuits

In this paper, we address the problem of verifying the equivalence of two sequential circuits. A hybrid approach that combines the advantages of BDD-based and ATPG-based approaches is introduced. Furthermore, we incorporate a technique called partial justification to explore the sequential similarity between the two circuits under verification to speed up the verification process. Compared with existing approaches, our method is much less vulnerable to the memory explosion problem, and therefore can handle larger designs. The experimental results show that in a few minutes of CPU time, our tool can verify the sequential equivalence of an intensively optimized benchmark circuit with hundreds of flip-flops against its original version.