Cheng-Lian Peng

On-line scheduling of real-time tasks for reconfigurable computing system

Efficient task scheduling is very important for obtaining high performance in reconfigurable computing system. Previous researches mostly concentrate on the spatial placement of tasks, and did not pay enough attention to temporal factors. This paper focuses on the on-line scheduling of real-time tasks with known executing time, and introduces the notion of recognition-complete for scheduling algorithms, that is the algorithm can arrange the start time of a newly arrived task as early as possible. A new on-line scheduling algorithm is proposed, which achieves recognition-complete by using the technique of time window. The simulation results show that the proposed algorithm gains a prominent improvement in scheduling performance over previous algorithms

SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model

Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable architecture with a unified software/hardware thread interface and high throughput point-to-point streaming structure. It supports dynamic computing resource allocation, runtime software/hardware switching, and streaming-based multithreaded management at the operating system level. SPREAD is designed to provide programmers of streaming applications with a unified view of threads, allowing them to exploit thread, data, and pipeline parallelism; it enhances hardware efficiency while simplifying the development of streaming applications for partially reconfigurable systems. Experimental results targeting cryptography applications demonstrate the feasibility and superior performance of SPREAD. Moreover, the parallelized Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Triple DES (3DES) hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.

A MDA based SoC Modeling Approach using UML and SystemC

Modeling is an efficient way to improve SoC design efficiency. In this paper, a Model Driven Architecture (MDA) based approach is proposed to combine the capability of newly released Unified Modeling Language 2.0 (UML) with SystemC, extending UML to express SystemC concept while maintaining the mappings between them. This approach will consequently promote stepwise semiautomatic conversion from UML specification to executable SystemC code. We intend to build a smooth SoC design flow in which implementation can be derived from specification directly. The proposed design flow will make use of the graphical modeling capability of UML, and produce SystemC code for further analysis.

A partially reconfigurable architecture supporting hardware threads

As a promising computing platform for stream processing, partially reconfigurable systems have shown their hardware efficiency and reconfiguration flexibility. This paper presents a partially reconfigurable architecture supporting hardware threads. It gives a unified software/hardware thread interface and high throughput point-to-point streaming structure. Dynamic computing resource allocation and streaming-based multi-threaded management are also provided at operating system level. It is easy for programmers to exploit the inherent thread, data and pipeline parallelism in a unified view of threads, enhancing hardware efficiency while improving productivity. The experimental results on a cryptography application demonstrate the feasibility and superior performance. Moreover, the parallelized AES, DES and 3DES hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units.

Fast On-Line Task Placement and Scheduling on Reconfigurable Devices

This paper focus on on-line placement and scheduling of tasks with known executing time on reconfigurable devices. The notion of recognition-earliest for scheduling algorithms is introduced, that is the algorithm can arrange the start time of a newly arrived task as early as possible. A new scheduling algorithm is proposed. By exploit the knowledge about temporal properties of each task, the algorithm attains recognition-earliest. A fast placement algorithm is also presented. The evaluation results show that the proposed placement algorithm is one of the fastest algorithm, and the proposed scheduling algorithm achieves the best performance compared with previous algorithms, while has a quite low runtime cost.

Online Hybrid Task Scheduling in Reconfigurable Systems

This paper mainly discusses online tasks scheduling problem on hybrid CPU-FPGA reconfigurable systems. In these systems, hybrid tasks may be binary codes executed on CPU as well as hardware logic circuits implemented on FPGA. Tasks scheduling algorithms of conventional operating systems are not suitable for scheduling hybrid tasks on CPU-FPGA architecture. Based on a real reconfigurable system prototype, we present a task scheduler model and correlative algorithm for scheduling software, hardware and hybrid tasks. This algorithm combines tasks allocation, tasks placement with tasks migration. Simulation results have demonstrated this algorithm provides preferable scheduling performance and reduces the scheduling rejection rate by making use of the great flexibility of hybrid tasks.

The Hardware Thread Interface Design and Adaptation on Dynamically Reconfigurable SoC

Nowadays, one of the challenges for creating a mixed hardware/software application on dynamically reconfigurable SoC is how to provide a unified programming model for hybrid hardware/software tasks and a portable interface adaptation for dynamically reconfigurable hardware tasks. In this paper, a POSIX-compliant hardware thread interface is proposed for data stream driven applications, serving for unified hardware/software multithread programming. At the same time, the stub/interface adaptation mechanism is also presented to support shared buffer based inter-thread communication/synchronization. At last, the experimental results on AES encryption/decryption hardware thread show that the interface design and adaptation could exploit programming transparency while effectively keep hardware efficiency.

A New Placement Approach to Minimizing FPGA Reconfiguration Data

Dynamic reconfiguration for fine-grained architectures is still associated with significant reconfiguration costs. In this paper, a new placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm is modified on the existing placement algorithm within VPR. It introduces the CLBs configuration of the previous circuit into cost function to increase similarity of CLBs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow, the proposed approach is validated by experiments on Xilinx Virtex FPGA platform, and experimental results show that the size of reconfiguration bitstream can be reduced.

The Design and Implementation of Hardware Task Configuration Management Unit on Dynamically Reconfigurable SoC

The advantages and the flexibility introduced into the hardware implementation by partial dynamic reconfiguration have rapidly changed the design flow of embedded systems. Configuration management is an important issue in operating system for dynamically reconfigurable system-on-chip. Reconfiguration overhead affects the performance of reconfigurable system. This paper presents a hardware implemented efficient configuration management unit. Wet define our operating system framework based on unified multitask programming model for reconfigurable system-on-chip at first. Then the detailed design and implementation of the configuration management unit are given. Finally a use case is presented, which shows the efficiency of the configuration.

A Co-design Flow for Reconfigurable Embedded Computing System with RTOS Support

Reconfigurable system provides both flexibility of software and performance of hardware. It is a significant trend in embedded application domain. Some new reconfigurable technologies and technology-dependent tools have been developed, but the whole design flow for run-time reconfigurable systems with real-time operating system support is not proposed. RTOS plays an important role in the system and the co-design flow. The special requirements for reconfigurable embedded systems with RTOS support are analyzed, and a novel co-design flow is proposed in this paper. A design case is presented here, which shows the co-design flows of the implementation of an adaptive signal filtering system on a commercially available reconfigurable platform. The results show that using run-time reconfiguration can save over 66% area when compared to a functionally equivalent fixed system and achieve 24 times speedup in processing time when compared with a functionally equivalent pure software design.