Jiarong Tong

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiplebit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100Mev-cm2/mg.

A Novel Hybrid FPGA Architecture

In this paper, a new hybrid field programmable gate array (FPGA) architecture is proposed. The logic tile, which consists of a logic cluster and related connection boxes (CBs), can be configured as either programmable logic arrays (PLAs) or look-up tables (LUTs). This architecture can be classified as AND-LUT array. PLAs are suitable for the implementation of large fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture (HFA) is more flexible to improve logic density. Experimental results based on MCNC benchmark circuits were performed between the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that 46% chip area is reduced using the new architecture

Uniform routing architecture for FPGA with embedded IP cores

A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines. Simulation results demonstrate our idea1.

FPGA ROUTING ARCHITECTURE OPTIMIZATION

This paper presents a versatile SB model with 4 sides. It is so versatile that it can cover various kinds of 4-side SB( in the following paper, we use SB for short) architectures in a 2-D FPGA. Base on this model, a new SB structure with better routability in segmented architecture is proposed. Comparing with Subset, Wilton and Universal SBs, it improves 10.1%, 3.3% and 4.6% separately. In addition, we propose a new segment distribution method in segmented architecture, which can greatly reduce circuits delay. With the same technical parameter, 10.4% average improvement in critical path is gained in a new distribution method than in VPRs when we use the universal SB

PAM Map: An architecture-independent logic block mapping algorithm for SRAM-based FPGAs

In this paper, we consider the general problem of mapping a given logic circuit onto an SRAM-based FPGA with programmable logic blocks of arbitrary architectures. We formulate the problem as a graph matching problem and present an architecture-independent algorithm for this purpose. This algorithm also obtains a best area saving of 4% compared to architecture-dependent methods.

A high utilization rate routing algorithm for modern FPGA

Different from older generation of FPGAs, routing resources of recent FPGAs are described by hierarchical general routing matrix (GRM). In this paper, we present a routing algorithm which utilizes routing resources more efficient for GRM based FPGAs. First, we build routing resource graph (RRG) by a bottom-up way, then we combine breadth-first search manner with A* directed by a certain proportion to enhance utilization rate of routing resources, and this routing algorithm has high-adaptability to latest FPGA routing architectures. The experiment result shows that the utilization rate of hex lines and long lines has been raised by 6% and 9% respectively.

Methodology of the design for segments-switchable switch blocks

Previous researches on switch blocks focused on the analysis of individual switch blocks that contain single length segments. In those switch blocks, segments of different length are separated from each other, which results in low efficiency and low speed. This paper presents a methodology to realize the switching between segments of different length. This methodology considers the design of switch blocks that contains segments of any length. Experimental evaluation is presented to show the 10% speed improvement that benefit from this methodology, with virtually no impact on area

An efficient packing algorithm based on constraint satisfaction problem technique

In this paper, an efficient packing algorithm based on constraint satisfaction problem technique is proposed for contemporary FPGA CLB architecture. No matter how complex the architecture is, there are a limited number of patterns, which can implement all functionalities of FPGA CLB logic. All the patterns are pre-designed and known as reference circuits. The proposed algorithm then matches the reference circuits from the given user logic circuit using specific constraints. Due to complex architecture of FPGA, to enumerate all the reference circuits in a fine-grain manner is impractical. Consequently, coarse-grain manner is adapted in the paper to overcome this problem. The experimental results show that the proposed algorithm achieves comparable performance in area and speed compared with literatures.

The Architecture of FDP FPGA Device

A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device contains 1,600 programmable logic cells, 160 programmable IO Blocks and 16 K bits dual port block RAM IP Core. It was fabricated with SMIC 0.18 mum Logic 1P6M Salicide 1.8 V/3.3 V process, its die size is 6.1times6.6 mm2, with the package of QFP208.