Cheng-Shing Wu

Modified vector rotational CORDIC (MVR-CORDIC) algorithm and architecture

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of CORDIC algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-CORDIC algorithm. Finally, we present two VLSI architectures for the MVR-CORDIC algorithm. It shows that by using the proposed MVR-CORDIC algorithm, we can save 50% execution time in the iterative CORDIC structure, or 50% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC scheme.

A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes

The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the angle recoding (AR) technique provides a relaxed approach to speed up the operation of the CORDIC algorithm. In this paper, we further apply the concept of AR technique to extend the elementary angle set in the microrotation phase. This technique is called the extended elementary-angle set (EEAS) scheme. The proposed EEAS scheme provides a more flexible way of decomposing the target rotation angle in CORDIC operation, and its quantization error performance is better than the AR technique. Meanwhile, to solve the optimization problem encountered in the EEAS scheme, we also proposed a novel search algorithm, called the trellis-based searching (TBS) algorithm. Compared with the greedy algorithm used in the conventional AR technique, the proposed TBS algorithm yields apparent signal-to-quantization-noise ratio (SQNR) improvement. Moreover, in the scaling phase of the EEAS-based CORDIC algorithm, we suggest a novel scaling operation, called Extended Type-II (ET-II) scaling operation. The ET-II scaling operation applies the same design concepts as the EEAS scheme. It results in much smaller quantization error than conventional Type-I scaling operation in the numerical approximation of scaling factor. By combining the aforementioned new schemes, the proposed EEAS-based CORDIC algorithm can improve the overall SQNR performance by up to 25 dB compared with previous works. Also, given the same target SQNR performance, we require only about 66% iteration number in the iterative CORDIC structure, or use 66% hardware complexity in the parallel CORDIC structure compared with conventional AR technique. Hence, high-performance/low-latency CORDIC very large-scale integration architectures can be achieved without degrading the SQNR performance.

A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach

Vector rotation is the key operation employed extensively in many digital signal processing applications. In this paper, we introduce a new design concept called Angle Quantization (AQ). It can be used as a design index for vector rotational operation, where the rotational angle is known in advance. Based on the AQ process, we establish a unified design framework for cost-effective low-latency rotational algorithms and architectures. Several existing works, such as conventional COordinate Rotational Digital Computer (CORDIC), AR-CORDIC, MVR-CORDIC, and EEAS-based CORDIC, can be fitted into the design framework, forming a Vector Rotational CORDIC Family. Moreover, we address four searching algorithms to solve the optimization problem encountered in the proposed vector rotational CORDIC family. The corresponding scaling operations of the CORDIC family are also discussed. Based on the new design framework, we can realize high-speed/low-complexity rotational VLSI circuits, whereas without degrading the precision performance in fixed-point implementations.

A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller

In this paper, a multi-path adaptive interpolated FIR (AIFIR)-based echo canceller is presented to perform the echo cancellation in full-duplex digital transmission over DSL. The proposed multi-path approach inherits the concept of the AIFIR-based echo canceller, where the long tail portion is modelled by an adaptive sparse FIR filter. A multi-path structure is addressed to break the inherent design tradeoffs in the conventional AIFIR-based echo canceller. More than one adaptive IFIR filter, modelling the corresponding tail portions of echo path, are employed. Also, an efficient implementation of the Image Compress Filter (ICF) is provided to reduce the complexity in performing the function of multi-ICFs. In addition, we apply the proposed scheme to the design of an echo canceller in an SHDSL transceiver. Computer simulations show that the flexible multi-path AIFIR-based echo canceller can reduce computational complexity 20% compared with previous works. About 60% complexity saving is obtained compared with the direct transversal implementation of an echo canceller.

A novel rotational VLSI architecture based on extended elementary angle set CORDIC algorithm

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the angle recoding (AR) technique provides a relaxed approach to speed up the operation of the CORDIC algorithm. In this paper, we further apply the concept of the AR technique to extend the elementary angle set in the micro-rotation phase. This technique is called the Extended Elementary-Angle Set (EEAS) scheme. The proposed EEAS scheme provides a more flexible way of decomposing the target rotation angle in CORDIC operation, and its quantization error performance is better than the AR technique. Meanwhile, we also propose an improved scaling operation, called Extended Type-II (ET-II) scaling operation, as the scaling scheme for the EEAS-based CORDIC algorithm. With the aid of the proposed EEAS scheme and ET-II scaling operation, we require only 39% iterations number in the iterative CORDIC structure, or use 39% hardware complexity in the parallel CORDIC structure compared with the conventional CORDIC approach. Hence, low-power/high-speed CORDIC VLSI architectures become feasible without sacrificing SQNR performance.

A novel trellis-based searching scheme for EEAS-based CORDIC algorithm

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. For applications that require forward rotation (or vector rotation) only, the extended elementary angle set (EEAS) Scheme provides a relaxed approach to speed up the operation of the CORDIC algorithm. When determining the parameters of EEAS-based CORDIC algorithm, two optimization problems are encountered. In the previous work, the greedy algorithm is suggested to solve these optimization problems. However, for an application that requires high-precision rotation operation, the results generated by the greedy algorithm may not be applicable. We propose a novel searching algorithm to overcome the aforementioned problem, called the trellis-based searching (TBS) algorithm. Compared with the greedy algorithm used in the conventional EEAS-based CORDIC algorithm, the proposed TBS algorithm yields apparent performance improvement. Moreover, the derivation of the error boundary as well as computer simulations are provided to support our arguments.

Modified vector rotational CORDIC (MVR-CORDIC) algorithm and its application to FFT

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the Modified Vector Rotational CORDIC (MVR-CORDIC) algorithm, to improve the speed performance of CORDIC algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of the CORDIC algorithm. In addition, three searching algorithms are suggested to find the corresponding directional and rotational sequences. In the example of a 128-point FFT, we have shown that by using the proposed MVR-CORDIC algorithm, the hardware complexity is only 33% compared with conventional CORDIC-based FFT. Meanwhile, the SQNR performance is 7 dB better than the conventional CORDIC approach.

Angle quantization approach for lattice IIR filter implementation and its trellis de-allocation algorithm

In a multiplier-less digital filter implementation, the sign-power-of-two (SPT) scheme can significantly reduce the hardware complexity but this may seriously degrade the filter performance due to the limited number of SPT terms. Since the CORDIC algorithm is similar to the SPT scheme in that they are both constructed by several shift-and-add operations, the performance would also be significantly affected by the number of these operations. In this paper, we propose the modified angle rotator (MAR) scheme; it provides a systematic solution to enhance the precision of quantized angle without additional hardware overhead. Furthermore, we also apply an appropriate optimization procedure, the trellis de-allocation algorithm, in the angle domain to further reduce the unnecessary operations. Our simulation results show that we can save 40% of the number of adders compared with the direct coefficient quantization approach in normalized lattice filter implementation.

A unified design framework for vector rotational CORDIC family based on angle quantization process

Vector rotation is the key operation employed extensively in many digital signal processing applications. We introduce a new design concept called angle quantization (AQ). It can be used as a design index for vector rotational operation, where the rotational angle is known in advance. Based on the AQ process, we establish a unified design framework for cost-effective low-latency rotational algorithms and architectures. Several existing works, such as conventional CORDIC, AR-CORDIC, MVR-CORDIC, and EEAS-based CORDIC, can be fitted into the design framework, forming a vector rotational CORDIC family. Based on the new design framework, we can realize high-speed/low complexity rotational VLSI circuits, whereas without degrading the precision performance in fixed-point implementations.

Cost-efficient multiplier-less FIR filter structure based on modified DECOR transformation

We propose a new design approach to implement an FIR filter using canonical sign digit (CSD) multipliers based on modified decorrelating transformation (MDECOR). The direct CSD approach will introduce serious quantization errors since the distribution of CSD numbers is very non-uniform. The proposed MDECOR transformation provides a systematic solution to reduce the dynamic range effectively. By combining the proposed MDECOR transformation followed by CSD quantization, we can avoid the aforementioned quantization problem. As a result, we do not need to employ additional non-zero bits to compensate for the distortion caused by direct CSD quantization, which helps to save the number of adders in VLSI implementations. Furthermore, the MDECOR transformation offers more freedom in the filter design. It can achieve high-precision performance under the same hardware complexity as the direct CSD approach. Our simulation results show that we can save 20% of the number of adders compared with the direct CSD approach.