Cheng-Zhou Zhan

An 8.29 mm

This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. This chip can be operated in 19 kinds of modes specified in Mobile WiMAX system, including block sizes of 576,..., 2304. There are four proposed design techniques: reordering of the base matrix, overlapped operations of main computational units, early termination strategy and multi-mode design strategy. Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of non-overlapped method, and the hardware utilization ratio can be enhanced from 50% to 75%. Besides, the proposed early termination strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values. The proposed multi-mode LDPC decoder design is implemented and fabricated in TSMC 0.13 mum 1.2 V 1P8M CMOS technology. The maximum operating frequency is measured 83.3 MHz and the corresponding power dissipation is 52 mW. The core size is 4.45 mm2 and the die area only occupies 8.29 mm2.

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In this paper, we propose a singular value decomposition (SVD) algorithm with superlinear-convergence rate, which is suitable for the beamforming mechanism in MIMO-OFDM channels with short coherent time, or short training sequence. The proposed superlinear-convergence SVD (SL-SVD) algorithm has the following features: 1) superlinear-convergence rate; 2) the ability of being extended smaller numbers of transmit and receive antennas; 3) being insensitive to dynamic range problems during the iterative process in hardware implementations; and 4) low computational cost. We verify the proposed design by using the VLSI implementation with CMOS 90 nm technology. The post-layout result of the design has the feature of 0.48 core area and 18 mW power consumption. Our design can achieve 7 M channel-matrices/s, and can be extended to deal with different transmit and receive antenna sets.

52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13

Singular value decomposition (SVD) is an optimal method to obtain spatial multiplexing gain in multi-input multi-output (MIMO) channels. However, the high cost of implementation and high decomposing latency of the SVD restricts its usage in current wireless communication applications. In this paper, we present a complete adaptive SVD algorithm and a reconfigurable architecture for high-throughput MIMO-orthogonal frequency division multiplexing systems. There are several proposed architectural design techniques: reconfigurable scheme, division-free adaptive step size scheme, early termination scheme, and data interleaving scheme. The reconfigurable scheme can support all antenna configurations in a MIMO system. The division-free adaptive step size and early termination schemes are used to effectively reduce the decomposing latency and improve hardware utilization. The data interleaving scheme helps to deal with several channel matrices concurrently. Besides, we propose an orthogonal reconstruction scheme to obtain more accurate SVD outputs, and then the system performance will be greatly enhanced. We apply our SVD design to the IEEE 802.11 n applications. This design is implemented and fabricated in UMC 90 nm 1P9M CMOS technology. The maximum operating frequency is measured to be at 101.2 MHz, and the corresponding power dissipation is at 125 mW. The core size is 2.17 mm2 and the die size occupies 4.93 mm2. The chip result shows that the average latency is only 0.33% of the wireless local area network coherence time. Hence, the proposed reconfigurable adaptive SVD engine design is very suitable for high-throughput wireless communication applications.

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For the applications of next-generation channel-adaptive communication systems, a real-time programmable LDPC decoder architecture is proposed with three design techniques: divided-group comparison (DGC), adaptive wordlength assignment (AWA), and efficient early termination scheme (EETS). By utilizing programmable principle, the hardware architecture can support arbitrary Quasi-Cyclic LDPC parity check matrices, including various locations of 1s, information bits, codeword lengths, and code rates. The prototyping LDPC decoder chip using 0.13um CMOS technology, which supports up to 23 code rates with a maximum block size of 1536 bits, only occupies 4.94 mm2 die area, operates at 125 MHz, and dissipates 58 mW power.

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Multiple-input multiple-output (MIMO) wireless communication systems with orthogonal frequency-division multiplexing (OFDM) achieve high spectral efficiency high channel capacity, and many MIMO-OFDM systems use the spatial multiplexing technique to improve the system performance. The MIMO-OFDM systems require the singular values and the corresponding singular vectors of the channel matrix by exploiting singular value decomposition (SVD). The information of the right singular-vector matrix can be fed back to the transmitter for linear precoding to improve the error performance when facing the channel matrix with rank deficiency problem. This work proposes a SVD algorithm with fast convergence speed, which is suitable for the MIMO channels with short coherent time. The proposed SVD algorithm has the following features: (1) low total computational complexity, (2) fast convergence speed, (3) the ability of reconfigurable to different numbers of transmitter and receiver antennas, and (4) insensitive to the dynamic range problem, which is suitable for hardware implementation.

Iterative Superlinear-Convergence SVD Beamforming Algorithm and VLSI Architecture for MIMO-OFDM Systems

This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power consumption. The core area is 4.45 mm2 and the die area is 8.29 mm2.

Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems

Codebook is a useful precoding technique for bandwidth limited systems because only few bits are required to feedback channel information. Many researchers propose several codebook selection criteria for linear receivers. However, these selection criteria are very computationally intensive, and most of them are not feasible for aperiodic feedback reporting in both LTE and LTE-Advanced (LTE-A) systems. Under the limited processing hardware and feedback delay constraints, low-complexity receivers with efficient codebook selection scheme are desirable. In this work, a low-complexity codebook searching engine is proposed to support both LTE and LTE-A operations. Also, it can be operated for both aperiodic and periodic feedback reporting. The properties and mutual correlations of the LTE and LTE-A codebooks are firstly analyzed. Then, a low-complexity grouping FFT-based codebook searching algorithm is proposed, which can be shared by LTE and LTE-A systems. Since the proposed algorithm is an algorithmic transformation, there is no performance loss. The proposed schemes have significant effect of reducing the number of multiplications by 56% compared with referenced works. Finally, a dual-mode low-complexity codebook searching engine with TSMC 90 nm is implemented. The IP size is 2.2 mm2 and the equivalent gate count is 547.6 K. The operating frequency is 125 MHz.

A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices

Color Doppler processing is one of the most important utility in the ultrasound imaging systems. Color Doppler imaging is mainly used to observe the blood flow in the region of interest. The desired blood signal will be greatly affected by the clutter and speckle noises, and it is the major design issues to eliminate these two kinds of noises effectively. In this work, we proposed a (1) joint-decision clutter filter and (2) motion-tracking adaptive persistence for effectively eliminating the clutter and speckle noises, respectively. The proposed two filters have individually 2~3 dB better performance than the referenced algorithms, and the proposed adaptive clutter filter and persistence can also work together in the same system to obtain even better performances.

High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems

This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10-6, the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm2 and 7.39 mm2, respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.

A 19-mode 8.29mm 2 52-mW LDPC Decoder Chipp for IEEE 802.16e System

In this paper, we propose a new scheduling algorithm for the overlapped message passing decoding, which can be applied to general low-density parity check (LDPC) codes. The partially parallel LDPC architecture is commonly used for reducing the area cost of the processing units. The dependency of two kinds of processing units, check node unit (CNU) and bit node unit (BNU), should be considered to enhance the hardware utilization efficiency (HUE). Based on the properties of the parity check matrix of LDPC codes, the updating calculation of the CNU and BNU can be overlapped to reduce the decoding latency by enhancing the HUE with the matrix scheduling algorithm. By applying our proposed LDPC scheduling algorithm to a (1944, 972)-irregular LDPC code, we can get about 60% throughput gain in average without any performance degradation.