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Dive into the research topics where An-Yeu Andy Wu is active.

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Featured researches published by An-Yeu Andy Wu.


IEEE Transactions on Computers | 2015

Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems

En-Jui Chang; Hsien-Kai Hsin; Chih-Hao Chao; Shu-Yen Lin; An-Yeu Andy Wu

The regular topology of mesh-based network-on-chip (NoC) provides flexible and scalable architecture for chip multiprocessor (CMP) systems. However, as the complexity of network increases, routing problems become performance bottlenecks. In the field of wide area networks (WANs), ant colony optimization (ACO) has been applied to an adaptive routing for improving performance and achieving load balancing. Nevertheless, if we directly apply ACO to NoC systems, the implementation cost of ACO is excessively high. To overcome this problem, the ACO-based adaptive routing must be reformulated while considering both router cost and NoC efficiency. This work proposes the regional ACO-based cascaded adaptive routing (RACO-CAR) scheme with the following techniques: 1) table elimination by removing redundant information, 2) table sharing by grouping pheromone information to merge table content, and 3) cascaded routing that assigns traffic to different uncongested regions to balance traffic. Our experimental results demonstrate that the RACO-CAR scheme has an improvement of 3.9-36.84 percent in saturation throughput compared with existing adaptive routing schemes. The implementation cost of the RACO-CAR router is only 37.4 percent of that of the ACO-based router with full routing table. Therefore, the proposed RACO-CAR scheme has high area efficiency, defined as saturation throughput divided by the total cost of router.


IEEE Transactions on Parallel and Distributed Systems | 2015

RC-Based Temperature Prediction Scheme for Proactive Dynamic Thermal Management in Throttle-Based 3D NoCs

Kun-Chih Chen; En-Jui Chang; Huai-Ting Li; An-Yeu Andy Wu

The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues in multicore systems using die stacking in recent days. Because of the larger power density and the heterogeneous thermal conductance in different silicon layers of 3D NoC, the thermal problems of 3D NoC become more exacerbated than that of 2D NoC and become a major design constraint for a high-performance system. To control the system temperature under a certain thermal limit, many Dynamic Thermal Managements (DTMs) have been proposed. Recently, for emergent cooling, the full throttling scheme is usually employed as the system temperature reaches the alarming level. Hence, the conventional reactive DTM suffers from significant performance impact because of the pessimistic reaction. In this paper, we propose a throttle-based proactive DTM(T-PDTM) scheme to predict the future temperature through a new Thermal RC-based temperature prediction (RCTP) model. The RCTP model can precisely predict the temperature with heterogeneous workload assignment with low constant computational complexity. Based on the predictive temperature, the proposed T-PDTM scheme will assign the suitable clock frequency for each node of the NoC system to perform early temperature control through power budget distribution. Based on the experimental results, compared with the conventional reactive throttled-based DTMs, the T-PDTM scheme can help to reduce 11.4~80.3 percent fully throttled nodes and improves the network throughput by around 1.5~211.8 percent.


2012 IEEE 6th International Symposium on Embedded Multicore SoCs | 2012

Path-Diversity-Aware Adaptive Routing in Network-on-Chip Systems

Yu-Hsin Kuo; Po-An Tsai; Hao-Ping Ho; En-Jui Chang; Hsien-Kai Hsin; An-Yeu Andy Wu

The partially adaptive routing plays an important role in the performance of Network-on-Chip (NoC). It uses information of the network to select a better path to deliver a packet. However, it may have imbalanced path diversity in different directions, which makes their tolerances of traffic load differ a lot from each other. This characteristic would cause problems in traffic balancing but give us extra information of the network. To achieve load balancing, in this paper, we present an adaptive routing scenario with Path-Diversity-Aware (PDA) and Augmented-PDA (A-PDA) selections, which use the information of path diversity. Moreover, we derive a formula to quantify the characteristic of path diversity. Experiments with different scenarios were conducted. The simulation results show that our proposed selections have an advantage over other selection functions in saturation throughput, with up to 36.84%, and have better scalability in large scale NoC. In addition, a low-cost router architecture is proposed to implement PDA and A-PDA and the synthesized results are also shown in this paper.


IEEE Transactions on Computers | 2015

Ant Colony Optimization-Based Adaptive Network-on-Chip Routing Framework Using Network Information Region

Hsien-Kai Hsin; En-Jui Chang; Kuan-Yu Su; An-Yeu Andy Wu

The network-on-chip (NoC) system can provide more scalable and flexible on-chip interconnection compared with system bus. The performance of on-chip adaptive routing algorithms greatly relies on the adopted network information. To the best our knowledge, previous routing algorithms utilize either spatial or temporal network information to improve performance. However, few works have established a framework on analyzing the network information nor showed how to integrate the spatial and temporal network information. In this paper, we define the network information region (NIR) framework for NoC systems. The NIR can indicate arbitrary combinations of network information and corresponding routing algorithms. We demonstrate how to apply NIR on analyzing the adaptive routing algorithms. To further demonstrate how NIR can help to integrate the spatial or temporal network information, we propose the ACO-based pheromone diffusion (ACO-PhD) adaptive routing framework based on the NIR. By diffusing the pheromone outward, spatial and temporal network information can be exchanged among adjacent routers. The range (i.e., size and shape) of the NIR is controllable by setting the parameters in the ACO-PhD algorithm. We show that we can reconfigure the ACO-PhD algorithm to each routing algorithm in its NIR subsets by adjusting the parameter settings. Finally, we implement and analyze the hardware design of corresponding router architecture. The results show an improvement of 4.86-16.93 percent on network performance and the highest area efficiency is achieved by the proposed algorithm.


IEEE Transactions on Parallel and Distributed Systems | 2017

Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems

Y.G. Chen; En-Jui Chang; Hsien-Kai Hsin; Kun-Chih Jimmy Chen; An-Yeu Andy Wu

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing (PDA-FTR) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.


signal processing systems | 2015

Low-complexity hybrid precoding algorithm based on orthogonal beamforming codebook

Wei-Lun Hung; Chiang-Hen Chen; Ching-Chun Liao; Cheng-Rung Tsai; An-Yeu Andy Wu

Millimeter wave (mmWave) communication system provides large unlicensed spectrum which helps to achieve huge capacity leap in the next-generation wireless system. The capacity is further improved by precoding technique in multiple-input-multiple-output (MIMO) transmission systems. Although the adoption of large antenna arrays in mmWave transceivers mitigates the huge path loss, it also increases hardware complexity of traditional digital precoding scheme. Hybrid precoding scheme, where signal is pre-processed in both analog and digital domains, is recently proposed to reduce the hardware cost. In this paper, an orthogonal beamforming codebook for two-dimensional (2D) channel environment is proposed to eliminate the efforts of searching for angle of departure (AoD). Then, by exploiting the orthogonality between beamforming vectors, a low-complexity algorithm of reconstructing hybrid precoder is proposed. Simulation results show that the proposed algorithm requires only 32% of complex multiplications compared with state-of-the-art approach, while suffering from less than 5% of performance loss.


signal processing systems | 2012

ACO-Based Deadlock-Aware Fully-Adaptive Routing in Network-on-Chip Systems

Kuan-Yu Su; Hsien-Kai Hsin; En-Jui Chang; An-Yeu Andy Wu

Ant Colony Optimization (ACO) is a problem-solving technique inspired by the behavior of real-world ant colony. ACO-based routing also has high potential on balancing the traffic load in the domain of Network-on-Chip (NoC), where the performance is generally dominated by traffic distribution and routing. Since the pheromone in ACO provides both spatial and temporal network information, we find ACO-based routing suitable for reducing the probability of deadlock and its penalty. With the three schemes inspired by the behavior of ants and named as ACO-based Deadlock-Aware Routing (ACO-DAR), our simulation shows that the occurrence of deadlock can be greatly suppressed and the network performance also improves as a consequence. Moreover, ACO-DAR makes use of the existing hardware of the original ACO-based routing, so the area overhead is minor and ACO-DAR is thus cost-effective.


international symposium on vlsi design, automation and test | 2014

Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems

Yuan-Sheng Lee; Hsien-Kai Hsin; Kun-Chih Chen; En-Jui Chang; An-Yeu Andy Wu

The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because of die stacking and different thermal conductance between layers. Up to now, most previous works cannot further achieve thermal balance of the 3D NoC systems since they consider either only temperature or only traffic information. We propose a Proactive Thermal-Dynamic-Buffer Allocation (PTDBA) scheme to constrain the routing resource around overheated regions. In addition, we reduce the frequency of packets switching in overheated router regions. By doing so, we can slow down the rate of temperature increment. Based on the proposed PTDBA, we can redistribute traffic load by means of buffer occupancy. The experimental results show that the proposed scheme can reduce the deviation of temperature distribution by 25.6% and help to improve network throughput in non-stationary irregular mesh by 74.8% compared with PTB3R.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2014

Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems

Hsien-Kai Hsin; En-Jui Chang; Chia-An Lin; An-Yeu Andy Wu

The advanced deep submicrometer technology increases the risk of failure for on-chip components. In advanced network-on-chip (NoC) systems, the failure constrains the on-chip bandwidth and network throughput. Fault-tolerant routing algorithms aim to alleviate the impact on performance. However, few works have integrated the congestion-, deadlock-, and fault-awareness information in channel evaluation function to avoid the hotspot around the faulty router. To solve this problem, we propose the ant colony optimization-based fault-aware routing (ACO-FAR) algorithm for load balancing in faulty networks. The behavior of an ant colony while facing an obstacle (failure in NoC) can be described in three steps: 1) encounter; 2) search; and 3) select. We implement the corresponding mechanisms as: 1) notification of fault information; 2) path searching mechanism; and 3) path selecting mechanism. With proposed ACO-FAR, the router can evaluate the available paths and detour packets through a less-congested fault-free path. The simulation results show that this paper has higher throughput than related works by 29.1%-66.5%. In addition, ACO-FAR can reduce the undelivered packet ratio to 0.5%-0.02% and balance the distribution of traffic flow in the faulty network.


signal processing systems | 2013

ACO-based fault-aware routing algorithm for Network-on-Chip systems

Chia-An Lin; Hsien-Kai Hsin; En-Jui Chang; An-Yeu Andy Wu

With the shrinking size of circuits and the scaling of Network-on-Chip (NoC), the on-chip components will have a higher chance to fail. The on-chip failures can cause traffic congestion and even system crash. To overcome this problem, the NoC routing algorithm should be implemented with fault-tolerant capability. Inspired by the fault-tolerant behavior of ant colony consisting of three steps: Encounter, Search, and Select, we propose Ant Colony Optimization-based Fault-aware Routing (ACO-FAR) algorithm for traffic balancing. To effectively forward the packets to a non-faulty region, three mechanisms of ACO-FAR correspond to the three-step behaviors of ants are proposed in this work. The simulation results show that proposed ACO-FAR has higher throughput than related works by 12.5%-77.7%. Also, this routing method improves the reachable packet ratio to 99.50%-99.98% and the distribution of traffic load in the faulty network.

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En-Jui Chang

National Taiwan University

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Hsien-Kai Hsin

National Taiwan University

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Huai-Ting Li

National Taiwan University

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Yu-Min Lin

National Taiwan University

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Ching-Chun Liao

National Taiwan University

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Kun-Chih Chen

National Taiwan University

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Ching-Yao Chou

National Taiwan University

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Hung-Yi Cheng

National Taiwan University

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Cheng-Rung Tsai

National Taiwan University

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Cheng-Zhou Zhan

National Taiwan University

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