Chengdi Xiao

A New Automatic Testing System Based on Image Processing and Microprobes for IC-Testing

In order to develop integrated circuit (IC) testing, a new system was suggested using a microprobe array, a four-wire tester, machine vision, and motion control technology. The microprobe array can be automatically aligned with the IC die by an image-processing program in the system. It was found that the operating efficiency of the algorithm was improved by six times by extracting the rectangular edge contour. Several image-processing methods were combined and optimized to calculate the deflection angle, and the linear fitting method was improved. Inaccurate fitting was eliminated by the modified fitting method, and the alignment error was significantly reduced. Although IC electrodes were precisely aligned with the microprobe tips, the compressive displacement of the microprobe also has a greater influence on the electrical testing. The testing resistance was not a stable value until the compressive displacement exceeded 100 μm. Finally, the effectiveness of the microprobe automatic testing approach was confirmed. The open circuits of the ICs can be detected, and the resistance of the circuits, which are not open circuits, can be automatically measured and evaluated.

An Electromechanical Model and Simulation for Test Process of the Wafer Probe

With the fast development of IC (integrated circuit) packaging industry, IC test is becoming more and more important, especially the probe test of the wafer packaging. Based on experimental data and theoretical analysis, an electromechanical model is first proposed to describe the characteristics of the testing process of wafer probe to understand the behavior of micro-probe testing process, and to simulate the whole physical process. The model consists of a dynamic mechanical model, a dc electro-mechanical coupling model and an ac impedance model, which is used to analyze the overall physical properties of the probe test process and has a good agreement with the experimental data. Based on the electromechanical model, a simulation platform is established first, which will provide a simulation tool for the design of the microprobe and setting of multiparameters.

Force-electrical characteristics of a novel mini-damper

In order to develop small loading and small damping, a small magneto-rheological fluid (MRF) damper with built-in magnetic coils is researched, and the dynamics model of new mini-damper is established based on testing the mechanical properties of the damper. It is found that the damping landing force adjustable range will be best when the damping gap is 1.5 mm. The loading force of the mini-damper is only 1.95 N–8.25 N by adjusting the coil current from 0 A–0.8 A. The smooth damping force is the third-order function with the current by polynomial fitting of the experimental data. The result of dynamics tests shows hysteresis damping characteristics, and an improved nonlinear dynamic model is proposed by combining with the structure characteristics. The parameters of the improved dynamic model are identified by using parameter identification and regression fitting. It will provide the basis for the application of the mini-MRF damper.

A Measurement Method on Nanoscale Thickness of the Ti Barrier Layer of TSV Structure for 3-D IC

As the characteristic dimension of an integrated circuit (IC) continuously scales down, together with the requirements of low power consumption, multiple functionality, and cost effectiveness, the conventional IC transforms into a 3-D IC. Through-silicon via (TSV) is a promising and preferred way to realize the reliable interconnection for a 3-D IC. Thus, accurate measurement of the critical structural parameters plays an important role in securing the integrity and reliability of TSV. In this paper, a novel image-processing-based measurement method is proposed to measure the barrier layer thickness and step coverage of TSV. Since the thickness of the barrier layer is generally less than 100 nm, which is a drawback of the conventional SEM method, we used the material information from SEM as well as structural prior of TSV to infer the barrier layer thickness on nanoscale. In addition, we further achieved the step coverage of thin films in TSV using the proposed measurement method.

Thermal conductivity of thin finite-size β-SiC calculated by molecular dynamics combined with quantum correction

Silicon carbide (SiC) is a most promising alternative material for the next generation of high-power and high-temperature devices duo to excellent performance, such as larger thermal conductivity compared with Silicon. The thermal conductivity of SiC bulk, as well as temperature dependence of thermal conductivity has been investigated in terms of simulations and experiments. However, when the characteristic size of materials is down to nanoscale, the thermal properties will be significantly different from bulk materials. Thus, it is important to understand the heat transport behavior of SiC thin films for developing nanoscale SiC devices. Nevertheless, thermal properties of SiC thin films have not been investigated systematically. In this paper, a non-equilibrium molecular dynamics model combined with quantum correction is presented for characterizing the thermal conductivity of thin finite-size β-SiC. Adopting the Tersoff empirical potential, temperature effect on thermal conductivity is predicted based on this model. It is found that the uncorrected lattice thermal conductivity diminishes evidently with decrease of temperature. Unlike the uncorrected results, the corrected results display a slight increase with temperature to a maximum value at ∼760 K This work provides a possible theoretical and computational basis for heat transfer and dissipation applications of nanoscale β-SiC thin film, and would also help the design of thermal barriers or new thermoelectric materials.

Investigation on the defect induced thermal mechanical stress for TSV

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. TSV based 3D IC packaging mainly consists of via formation, via filling, wafer thinning and chip stacking. Copper is one of the most commonly used materials for via filling which is a significant process and challenge in TSV manufacturing processes. However, defects introduced during copper filling process would induce some reliability problems. In this paper, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of defects for TSV thermal mechanical stress. Specifically, the defects in the shape of circle, square and triangle were built in the TSV model, respectively. Then, the effect of defects with different shape on thermal stress distribution were investigated. Moreover, the impact of the size and location of the defect on thermal stress was also studied. Simulation results show that thermal stress distribution in TSV is distinct with the different shape and location of defect. Additionally, the maximum equivalent stress of the TSV with triangular or square defect increases as the increase of the size of defect.

Investigation on the effect of multiple parameters towards thermal management in 3D Stacked ICs

Three dimensional (3D) integration technology, involving the vertical stacking of multiple chips using through-silicon vias (TSVs), has emerged as a promising solution to improve the performance of microelectronic devices. However, the complex structures and the consequent increase in power density exacerbate the challenge of thermal management in the device including multiple chips. In order to ensure the reliability of 3D stacked chips during operation, it is important to have a better understanding of the thermal distribution of a 3D chip stack. In this paper, a detailed analysis of 3D IC packaging from thermal reliability perspective is presented, performed by finite element simulations. The effect of the variation of structure-related parameters on steady-state temperature profiles in the stack has been analyzed, including TSVs diameter and pitch, the thickness of SiO2, as well as the thermal conductivity of under fill. The research provides useful insights for thermal management of 3D IC packaging.