Hu He

The soft-landing features of a micro-magnetorheological fluid damper

The authors demonstrate that the micro magneto-rheological fluid device is designed by the method of outer magnetic coil to generate a mechanical loading less than 20 N. The results confirm that the method can obtain miniature device easily and control the magnetic field conveniently. The magnetic field, the channel gap, and the initial position of valve plug were optimized by finite element simulation and experimental test. Additionally, an impact force at the beginning can be eliminated by using a modeled synchronous linear current, which indicates that the micro-magnetorheological fluid damper has good soft-landing performance.

Structural Design and Control of a Small-MRF Damper Under 50 N Soft-Landing Applications

To achieve less than 50 N soft-landing using magneto-rheological fluid (MRF) damper, a novel small-MRF damper has been developed. First, we design a new outer electromagnetic coil comparing with traditional inner coil structure, which can obtain miniature damper easily and control the magnetic field conveniently. Second, we apply silicon steel rather than carbon steel for MRF damper, which can improve the performance of response and demagnetization of the damper. The effectiveness of the innovative design is confirmed by experiments in this paper. The range of soft-landing load can be controlled from 18 to 55 N by adjusting the coil current from 0 to 0.8 A. Additionally, an impact force at the beginning can be eliminated using a modeled synchronous linear current, which indicates that the small-MRF damper has good soft-landing performance. Furthermore, the novel approach provides developing ideas for the miniaturization of the MRF damper.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Abstract Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

A Measurement Method on Nanoscale Thickness of the Ti Barrier Layer of TSV Structure for 3-D IC

As the characteristic dimension of an integrated circuit (IC) continuously scales down, together with the requirements of low power consumption, multiple functionality, and cost effectiveness, the conventional IC transforms into a 3-D IC. Through-silicon via (TSV) is a promising and preferred way to realize the reliable interconnection for a 3-D IC. Thus, accurate measurement of the critical structural parameters plays an important role in securing the integrity and reliability of TSV. In this paper, a novel image-processing-based measurement method is proposed to measure the barrier layer thickness and step coverage of TSV. Since the thickness of the barrier layer is generally less than 100 nm, which is a drawback of the conventional SEM method, we used the material information from SEM as well as structural prior of TSV to infer the barrier layer thickness on nanoscale. In addition, we further achieved the step coverage of thin films in TSV using the proposed measurement method.

Thermal conductivity of amorphous SiO 2 thin film: A molecular dynamics study

Amorphous SiO2 (a-SiO2) thin films are widely used in integrated circuits (ICs) due to their excellent thermal stability and insulation properties. In this paper, the thermal conductivity of a-SiO2 thin film was systematically investigated using non-equilibrium molecular dynamics (NEMD) simulations. In addition to the size effect and the temperature effect for thermal conductivity of a-SiO2 thin films, the effect of defects induced thermal conductivity tuning was also examined. It was found that the thermal conductivity of a-SiO2 thin films is insensitive to the temperature from −55u2009°C to 150u2009°C. Nevertheless, in the range of the thickness in this work, the thermal conductivity of the crystalline SiO2 (c-SiO2) thin films conforms to the T−α with the exponent range from −0.12 to −0.37, and the thinner films are less sensitive to temperature. Meanwhile, the thermal conductivity of a-SiO2 with thickness beyond 4.26u2009nm has no significant size effect, which is consistent with the experimental results. Compared with c-SiO2 thin film, the thermal conductivity of a-SiO2 is less sensitive to defects. Particularly, the effect of spherical void defects on the thermal conductivity of a-SiO2 is followed by Coherent Potential model, which is helpful for the design of low-K material based porous a-SiO2 thin film in microelectronics.

Comparison of Darveaux model and Coffin-Manson model for fatigue life prediction of BGA solder joints

The reliability of interconnections in microelectronic packages is an urge concern for the well-functioned electronic devices. Owing to the mismatch of CTE of different materials involved in the interconnections, the structures endures high risk of fatigue failure under thermal cycle loading. Numerous fatigue life prediction models have been proposed or developed for the evaluation of reliability of interconnections, e.g., solder joints, under thermal cyclic loadings. Particularly, energy-based Darveaux model and strain-based Coffin-Manson model are two widely employed to predict fatigue life for BGA solder balls. In this paper, the fatigue life prediction results of solder balls in BGA packaging using Darveaux model and C-M model have been compared and discussed, varied geometric size have been deployed to further explore the performance of two selected fatigue models. Simulation results show that the predictive life of Darveaux model above the other one. Additionally, in both models, fatigue life increase while the height increase and decrease with the diameter increase, although the trends are slightly different.

Thermal conductivity of thin finite-size β-SiC calculated by molecular dynamics combined with quantum correction

Silicon carbide (SiC) is a most promising alternative material for the next generation of high-power and high-temperature devices duo to excellent performance, such as larger thermal conductivity compared with Silicon. The thermal conductivity of SiC bulk, as well as temperature dependence of thermal conductivity has been investigated in terms of simulations and experiments. However, when the characteristic size of materials is down to nanoscale, the thermal properties will be significantly different from bulk materials. Thus, it is important to understand the heat transport behavior of SiC thin films for developing nanoscale SiC devices. Nevertheless, thermal properties of SiC thin films have not been investigated systematically. In this paper, a non-equilibrium molecular dynamics model combined with quantum correction is presented for characterizing the thermal conductivity of thin finite-size β-SiC. Adopting the Tersoff empirical potential, temperature effect on thermal conductivity is predicted based on this model. It is found that the uncorrected lattice thermal conductivity diminishes evidently with decrease of temperature. Unlike the uncorrected results, the corrected results display a slight increase with temperature to a maximum value at ∼760 K This work provides a possible theoretical and computational basis for heat transfer and dissipation applications of nanoscale β-SiC thin film, and would also help the design of thermal barriers or new thermoelectric materials.

Investigation on the defect induced thermal mechanical stress for TSV

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. TSV based 3D IC packaging mainly consists of via formation, via filling, wafer thinning and chip stacking. Copper is one of the most commonly used materials for via filling which is a significant process and challenge in TSV manufacturing processes. However, defects introduced during copper filling process would induce some reliability problems. In this paper, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of defects for TSV thermal mechanical stress. Specifically, the defects in the shape of circle, square and triangle were built in the TSV model, respectively. Then, the effect of defects with different shape on thermal stress distribution were investigated. Moreover, the impact of the size and location of the defect on thermal stress was also studied. Simulation results show that thermal stress distribution in TSV is distinct with the different shape and location of defect. Additionally, the maximum equivalent stress of the TSV with triangular or square defect increases as the increase of the size of defect.

Investigation on the effect of multiple parameters towards thermal management in 3D Stacked ICs

Three dimensional (3D) integration technology, involving the vertical stacking of multiple chips using through-silicon vias (TSVs), has emerged as a promising solution to improve the performance of microelectronic devices. However, the complex structures and the consequent increase in power density exacerbate the challenge of thermal management in the device including multiple chips. In order to ensure the reliability of 3D stacked chips during operation, it is important to have a better understanding of the thermal distribution of a 3D chip stack. In this paper, a detailed analysis of 3D IC packaging from thermal reliability perspective is presented, performed by finite element simulations. The effect of the variation of structure-related parameters on steady-state temperature profiles in the stack has been analyzed, including TSVs diameter and pitch, the thickness of SiO2, as well as the thermal conductivity of under fill. The research provides useful insights for thermal management of 3D IC packaging.