Chenglian Peng

An operating system framework for reconfigurable systems

Reconfigurable computing have been accepted as vehicles for both achieving potentially much higher performance than software and maintaining a higher level of flexibility than hardware. However, there is still no much operating system support for it. Based on the essential differences between software-tasks and hardware-tasks, this pa-per presents and implements a RTOS for reconfigurable systems using uniform multitask model, called SHUM-UCOS (software-tasks hardware-tasks uniform management UCOS) , which is designed with the UCOSII as prototype. This RTOS traces and manages the usage of re-configurable resources (FPGAs). and can improve the utilization of these resource and the parallelism of the tasks with the hardware-tasks preconfiguration. And it has been proved by experiments that SHUM-UCOS can shorten the migration time from software implements to hardware implements with the performance improvement.

SHUM-uCOS: A RTOS using multi-task model to reduce migration cost between SW/HW tasks

The design of embedded systems has become more complex than ever, and the design qualities depend more on the cooperation of multidisciplinary design teams: hardware engineers and software engineers in general. However, due to the lack of uniform programming model and system components for these different teams, the migrations costs of a function model from software to hardware are high. But these actions are necessary in the hardware-software partitioning of embedded systems, especially in the prototype designs. To cope with this problem, we adopt a uniform multi-task model and implement a RTOS (real-time operating system), called SHUM-uCOS, which deals with hardware functions as same as software tasks. This RTOS uses uCOSII as its prototype, traces and manages the states of reconfigurable resources (FPGAs), which allows the execution of hardware tasks in a true multitasking manner. Moreover, SHUM-uCOS also defines a standard hardware-task interface, which supports share-bus protocol. It has been proved by experiments that SHUM-uCOS can shorten the migration time from software implementations to hardware implementations with the performance improvement.

Fast on-line real-time scheduling algorithm for reconfigurable computing

Partially reconfigurable devices are able to execute several tasks in parallel and allow for on-line reconfiguration. To manage such devices at runtime, the scheduler in the operating system has two more modules for hardware tasks: placer and loader. Placer is to find appropriate places in reconfigurable devices and loader is to do the reconfiguration for hardware tasks. In order to satisfy the timing constraints in hard real-time systems, we propose a fast online real-time scheduling algorithm. Our algorithm will be based on correct empty resource management and will utilize the reconfiguration reuse. The experiments show that the developed scheduler leads to substantial performance gains.

An automatic test coverage analysis for SystemC description using aspect-oriented programming

This work addresses the problem of functional verification starting from a high level description of the system under test, specified in SystemC. The verification method considered is based upon the simulation of executable SystemC description. Test coverage analysis is the main technique for checking and showing that the testing has been thorough. We propose an approach to automate the coverage analysis using aspect-oriented programming. Aspects here are described as checkers for detecting coverage. The most important feature using the aspect-oriented technology here is that allows checking functions across classes to be added or replaced without modifying the original code. UML2.0 is used to model the dynamic behavior view of SystemC description as a coverage metric model. Inherently, it is possible to automate the whole test coverage analysis using our methodology.

A concurrent design approach for data flow dominated embedded systems

The increased complexity and short life cycle of todays embedded systems increase the need of more aggressive methodology capable of designing systems quicker and more easily. In this paper, with the help of dynamic data flow modeling technique and a component-oriented implementation architecture, we present a concurrent design approach for data flow dominated embedded system. The approach can decompose the design process of an embedded system into a lot of separate design items with the consistency being maintained. The generation of implementation code framework for hardware/software components and implementation code for different types of data paths not only accelerates the design process, but also provides a guarantee for the integrity of the target system.

Reduce SW/HW migration efforts by a RTOS in Multi-FPGA systems

The boundary between software and hardware is becoming blurry in modern embedded systems, especially in reconfigurable computing systems. It makes an easy-to-use design space explorer more important than ever for engineers. This paper proposes a RTOS (Real-Time Operating System) to reduce design efforts while migrating functions between software and hardware. The RTOS provides reconfigurable hardware threads with identical API interfaces and data structures, just like those for software threads. To utilize reconfigurable resources efficiently, the states of threads are controlled and managed by the RTOS. Threads can also be preconfigured according to static DFGs (data flow graphs). Experiments on the Rhealstone benchmark have shown that multi-thread environments provided by the proposed RTOS can extend the scale of traditional operating systems and give designers more freedom to perform design space exploration.

System-on-chip design with dataflow architecture

This work presents a practical approach to implement dataflow dominated system-on-chip system with real-time requirements. With dataflow model and a virtual component (VC)-oriented implementation architecture, the approach has the advantages of effectively supporting design reuse or reconfiguration. Single bus architecture reduces the design complexity and implementation cost and provides an effective way to meet real-time constraints. Based on the architecture some important aspects such as bus arbitrating, VC framework are described, these techniques are critical factors for achieving design goal.

Component priority assignment in the data flow dominated embedded systems with timing constraints

Dataflow dominated embedded systems often use data flow graphs (DFG) as system models. To achieve the desired performance, these systems usually contain a lot of hardware/software components working in parallel. These concurrent and cooperative components result in the contentions for shared resources due to architecture and data dependencies. The approach to solve the contentions can be priority assignments. In this paper we introduce an algorithm which can find out a priority assignment for a given set of components working in parallel with a timing constraint. In addition, the algorithm also provides a fast way to calculate, whether a set of components working in parallel can guarantee a given timing constraint. Hence the algorithm can be applied both in designing phase and implementation phase of hardware/software co-design for embedded systems.

ESIDE - embedded system integrated design environment based on Eclipse platform

Traditional embedded system design procedure involves a mixture of design tools to cope with software and hardware design at several abstract levels. Data exchange between tools and cooperation between designers are difficult in such environment. This paper presents an embedded system integrated design environment (ESIDE), which applies a top-down design flow and integrates design tools at different abstract levels. It provides a consistent mechanism for the data exchange between tools and an efficient way to manage various kinds of intellectual property (IP) components with an IP database. ESIDE supports design exchange and management between various designers so that a large number of designers are able to collaborate efficiently in a complex embedded system design.

A CSCWD framework for component-based SOC design

Silicon technology now allows designers to build chips consisting of tens of millions of transistors. This technology promises new levels of system integration onto a single chip (system-on-chip, SOC), but also presents significant challenges to the chip designers. In order to implement such systems, designers are increasingly relying on reuse of intellectual property (IP) components. Component-based SOC design (CBSD) becomes one of the most effective solutions to improve system development quality and productivity. In a complex SOC design, multiple engineering design teams are required to work cooperatively in order to design a product, each team may focus on only a part of the whole system. So component exchange, configuration and integration are the core technologies and frontier research areas in CBSD. This work presents a CSCWD framework based on extensible markup language (XML) specification for IP component exchange and integration.