Chenkun Wang

A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time (tr) and duration (td) was performed across a wide temperature range (T = -30/+110°C). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length (L), width (W), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

A Dual-Polarity Graphene NEMS Switch ESD Protection Structure

Conventional on-chip electrostatic discharge (ESD) protection structures for integrated circuits (ICs) rely on in-Si p-n-junction-based devices, which have many inherent disadvantages unsuitable for ICs at nanonodes. This letter reports a novel above-IC graphene-based nanoelectromechanical system (gNEMS) transient switch ESD protection mechanism and structure. Transmission line pulse testing shows dual-polarity transient ESD switching effect with a response time down to 200 ps. This gNEMS switch is a potential ESD protection solution to realize the above-Si ESD protection designs through 3-D integration in IC back end of line.

TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection

Compact and robust electrostatic discharging (ESD) protection structures are critical to on-chip ESD protection for ICs. Conventional in-Si ESD protection structures have many disadvantages. A new above-IC graphene NEMS (gNEMS) switch is reported as an ESD protection structure, which features almost zero leakage and robust ESD protection. A systematic characterization of gNEMS ESD structures was conducted by transient transmission line pulse (TLP) testing. The statistical analysis reveals the relationship between ESD discharging behaviors and the influences of gNEMS device dimensions and TLP testing conditions on ESD discharging.

Systematic transient characterization of graphene interconnects for on-chip ESD protection

Both novel ESD structures and robust ESD interconnects are critical to on-chip ESD protection designs [1-3], which are characterized by transient transmission line pulse (TLP) testing for human body model (HBM). Compared to metal lines (Al & Cu), graphene ribbons (GR) has great potential as robust ESD interconnects due to its excellent thermal and mechanical properties. We report the first systematic characterization and statistical analysis of CVD grown-graphene by transient TLP testing with varying pulse rise time (tr) and duration (td) at different temperature. The statistics suggest that GR wires are potential candidates for ESD interconnects for future on-chip ESD protection designs.

A 2.22–2.92GHz LC-VCO demonstrated with an integrated magnetic-enhanced inductor in 180nm SOI CMOS

We demonstrate a 2.22-2.92GHz LC voltage-controlled oscillator (LC-VCO) in an 180nm SOI CMOS integrated with a novel compact inductor with vertical magnetic core. The new magnetic-enhanced inductor was fabricated using a new CMOS-compatible process. Measurements show that the single-layer magnetic-cored inductor increases its inductor density by 16.9% within the operation frequency range, leading to a phase noise reduction for the VCO from -106.97dBc/Hz to -113.49dBc/Hz at 10MHz offset frequency. This VCO prototype demonstrates the potential of designing RF system-on-a-chip (SoC) using new vertical magnetic-cored inductors.

More-Than-Moore: 3D heterogeneous integration into CMOS technologies

Monotonic scaling-down of CMOS integrated circuit (IC) technologies is rapidly approaching to its physical end, yet advances in ICs will continue. Instead of one-dimensional (1D) scaling dawn, one apparent solution is lateral integration of heterogeneous devices in 3-dimensional (3D) fashion, which opens great opportunities to make more complex Si-based microsystems for unlimited applications well beyond ICs, such as, internet of things (IoT). This paper discusses 3D heterogeneous integration of a few non-traditional devices into traditional Si CMOS technologies.

Key note: Integrated design-for-reliability for ICs

This paper reviews historical development of on-chip electrostatic discharging (ESD) protection designs for ICs. ESD failure is the biggest reliability challenge to ICs. On-chip ESD protection is the core for integrated design-for-reliability (iDfR), which is required for the advanced ICs and microsystems. This review discusses the past, current and future of on-chip ESD protection designs.

Characterization and analysis of diode-string ESD protection in 28nm CMOS by VFTLP

This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VFTLP) tester for Charged Device Model (CDM) ESD protection. The analysis results reveal the I-V insights critical to practical ESD protection designs.

A comparison study of DTSCR by TCAD and VFTLP for CDM ESD protection

This paper reports a study of transient behaviors of diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharging (ESD) protection structures for ultra-fast Charged Device Model (CDM) ESD protection. The DTSCR ESD protection structures, fabricated in a 28nm CMOS process, were characterized using a new combined Very Fast Transmission Line Pulse (VFTLP) testing and TCAD simulation approach, which resolves the deficiency problem of VFTLP testing due to the effects of ultra-short duration of CDM ESD pulse waveforms. The result reveals critical difference of DTSCR behaviors under VFTLP and real CDM ESD that gives a better evaluation of overshooting, turn-on time, turn-on delay, etc.