Feilong Zhang

A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs.

Systematic Characterization of Graphene ESD Interconnects for On-Chip ESD Protection

We report systematic transient characterization of a graphene ribbon (GR) used as an interconnect for electrostatic discharge (ESD) protection of future integrated circuits. A large set of GR wires (around 6000) with varying and practical dimensions were fabricated using the chemical vapor deposition method and characterized by transmission line pulsing (TLP) and very fast TLP (VFTLP) measurements. Comprehensive TLP and VFTLP testing with varying pulse rise time (tr) and duration (td) was performed across a wide temperature range (T = -30/+110°C). Measurement-based statistics reveal the relationship between ESD capability of GR wires and the wire length (L), width (W), and number of graphene layers, as well as ESD pulse shapes and operation temperature.

TLP measurement and analysis of graphene NEMS switches for on-chip ESD protection

Compact and robust electrostatic discharging (ESD) protection structures are critical to on-chip ESD protection for ICs. Conventional in-Si ESD protection structures have many disadvantages. A new above-IC graphene NEMS (gNEMS) switch is reported as an ESD protection structure, which features almost zero leakage and robust ESD protection. A systematic characterization of gNEMS ESD structures was conducted by transient transmission line pulse (TLP) testing. The statistical analysis reveals the relationship between ESD discharging behaviors and the influences of gNEMS device dimensions and TLP testing conditions on ESD discharging.

More-Than-Moore: 3D heterogeneous integration into CMOS technologies

Monotonic scaling-down of CMOS integrated circuit (IC) technologies is rapidly approaching to its physical end, yet advances in ICs will continue. Instead of one-dimensional (1D) scaling dawn, one apparent solution is lateral integration of heterogeneous devices in 3-dimensional (3D) fashion, which opens great opportunities to make more complex Si-based microsystems for unlimited applications well beyond ICs, such as, internet of things (IoT). This paper discusses 3D heterogeneous integration of a few non-traditional devices into traditional Si CMOS technologies.

Key note: Integrated design-for-reliability for ICs

This paper reviews historical development of on-chip electrostatic discharging (ESD) protection designs for ICs. ESD failure is the biggest reliability challenge to ICs. On-chip ESD protection is the core for integrated design-for-reliability (iDfR), which is required for the advanced ICs and microsystems. This review discusses the past, current and future of on-chip ESD protection designs.

Characterization and analysis of diode-string ESD protection in 28nm CMOS by VFTLP

This paper reports characterization and analysis of diode string electrostatic discharging (ESD) protection structures fabricated in a foundry 28nm CMOS technology. Comprehensive measurements were conducted using very-fast transmission line pulse (VFTLP) tester for Charged Device Model (CDM) ESD protection. The analysis results reveal the I-V insights critical to practical ESD protection designs.

A comparison study of DTSCR by TCAD and VFTLP for CDM ESD protection

This paper reports a study of transient behaviors of diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharging (ESD) protection structures for ultra-fast Charged Device Model (CDM) ESD protection. The DTSCR ESD protection structures, fabricated in a 28nm CMOS process, were characterized using a new combined Very Fast Transmission Line Pulse (VFTLP) testing and TCAD simulation approach, which resolves the deficiency problem of VFTLP testing due to the effects of ultra-short duration of CDM ESD pulse waveforms. The result reveals critical difference of DTSCR behaviors under VFTLP and real CDM ESD that gives a better evaluation of overshooting, turn-on time, turn-on delay, etc.

Circuit-level ESD protection simulation using behavior models in 28nm CMOS

Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events. The new ESD circuit simulation method is validated using ICs designed and fabricated in 28nm CMOS.

Transient characterization of graphene NEMS switch ESD protection structures

Above-IC graphene NEMS (gNEMS) switch electrostatic discharge (ESD) protection structures are designed to replace traditional in-Si PN-based ESD structures. Built in CMOS back-end without PN junctions, gNEMS eliminates ESD-induced parasitics (leakage, capacitance, noise) inherent to PN junctions. Transient characterization of gNEMS ESD structures were conducted by transmission line pulsing (TLP) measurement to understand impacts of zapping waveforms on ESD behaviors. gNEMS ESD switch is a potential ESD protection solution to advanced ICs at nano nodes.

In-Die Through-BEOL Metal Wall for Noise Isolation in 180-nm FD-SOI CMOS

This letter reports a conceptual in-die through-back-end-of-the-line metal wall structure for noise isolation demonstrated in a foundry 180-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. The near-closed-loop isolation wall was made of a trench ring etched by focused ion beam and filled with silver nano powder in a post-CMOS process module developed. Crosstalk suppression was confirmed in measurement that shows a reduction of around 9 dBm in the third-order intermodulation interferers as predicted full-wave electromagnetic co-simulation. The structure can be readily integrated into the foundry technologies as a potential crosstalk reduction solution for mixed-signal integrated circuits in FD-SOI CMOS processes.