Chenxi Zhao

Analysis and Equivalent-Circuit Model for CMOS On-Chip Multiple Coupled Inductors in the Millimeter-Wave Region

A growing number of on-chip inductors have been applied in the millimeter-wave IC design. The coupling effects between them have a negative impact on the performance of the circuit and each on-chip inductor. In this paper, a new equivalent-circuit model and a parameter extraction method for multiple on-chip inductors in the millimeter-wave region are proposed. The impacts of coupling effects on every onchip inductor are comprehensive considered in the proposed parameter extraction method. The characteristics of the multiple on-chip-coupled inductors are analyzed, modeled, and measured. The test structures were fabricated by 0.18-μm and 90-nm CMOS processes. The inductances, quality factors, and S-parameters of the model agree well with the measured performance of on-chip-nested and side-by-side-coupled inductors over a wide frequency range from 10 MHz up to millimeter-wave frequency band.

A Broadband and Equivalent-Circuit Model for Millimeter-Wave On-Chip M:N Six-Port Transformers and Baluns

A new equivalent-circuit model and parameter-extraction method for six-port M:N on-chip transformers and baluns are presented in this paper. All of the elements in the proposed model are extracted directly by S-parameters based on full-wave electromagnetic (EM) simulations. Series branches in the model are used to capture the characteristics of the primary and secondary windings. The shunt impedance networks on the terminals represent the substrate loss. The magnetic coupling effects of windings are denoted by six mutual inductances. The electrical coupling effects are represented by mutual capacitances. In this paper, we have developed a parameter-extraction methodology for mutual inductances of six-port transformers. The proposed model and parameters extraction methodology are verified with a number of six-port transformers with different turn ratio by measurements and full-wave EM simulations. The proposed model shows good agreement with measured data over a wide frequency band.

A Ku band 4-Element phased array transceiver in 180 nm CMOS

A Ku Band (15∼18 GHz) 4-Element (4 Transmitters/4 Receivers) fully differential phased array transceiver is designed and fabricated using a 180nm CMOS process. The proposed phased array integrated with T/R switches and SPI controller is based on an all-RF structure. TX and RX channels are placed side-by-side to improve integration density and isolation. Each channel consists of a 5-bit phase shifter and a 4-bit attenuator. The measured maximum gain is 21 dB for a TX channel and 10.8 dB for a RX channel. The minimum noise figure of RX with T/R switch is 9.9 dB. The input referred PidB of RX is −14.5 dBm at 16GHz, while the output referred PidB of transmitter is 10 dBm at 16 GHz. Additionally, the RMS phase error of phase shifter is less than 4o, and the RMS amplitude error of attenuator is less than 3.2 dB. A RX element draws 114 mA from a 1.8 V supply, while a TX element consumes 145 mA with a 3.3V supply. The chip occupies 4.5∗5mm2 area including pads.

Analysis and Design of CMOS Doherty Power Amplifier Based on Voltage Combining Method

The impedance at the each input terminal of paper presents a voltage combining Doherty power amplifier in a standard 180-nm CMOS process. This Doherty PA uses a series combining transformer (SCT) to combine the output power and realize the load modulation, which is different from the conventional current combining method. The series combining transformer is analyzed for impedance modulation behavior, and we have provided the design method. The proposed Doherty PA achieves a maximum output power of 27.6 dBm at 1.75 GHz with a peak power added efficiency (PAE) of 35.2% at 3.4 V supply voltage. The PAE at 6 dB back-off is still high, about 29.2%. The PA has 24.2 dBm output power with 30.2% PAE at −37 dBc ACLR (5 MHz offset) and 25.2 dBm output power with 32% PAE at −33 dBc ACLR (5 MHz offset) at 1.75 GHz under a wideband code division multiple access signal with 3.3-dB PAPR and 3.84-MHz BW.

A Ku-band CMOS LNA with transformer feedforward gm-boosting technique

This paper presents the design of a Ku-band CMOS low noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedforward gm-boosting technique is employed in a single-ended common-gate LNA to reduce the noise figure (NF) and improve the gain simultaneously. A single cascode is the second stage of the LNA. Fabricated in 0.18um RF CMOS process, the LNA exhibits a minimum noise figure (NF) of 3.6 dB at 17.5 GHz and a highest power gain of 18 dB at 17.5GHz in measurement. The LNA only consumes 7mA from a power supply of 1.8V and the total area of this design is 0.6*0.8 mm2.

A 24 GHz enhanced neutralized cascode LNA with 4.7 dB NF and 19.8 dB gain

This paper presents a two-stage low noise amplifier (LNA) for 24GHz automotive radar applications. Compared with traditional common source (CS) stage, the neutralized topology is used to improve the gain and reverse isolation in the first stage. In the second stage, an enhanced neutralized technique is adopted to improve the gain further. The LNA is fabricated by using standard 180-nm CMOS technology and occupies a chip area of 1.0 × 0.8mm2. The design realizes a gain of 19.8 dB, a noise figure (NF) of 4.7 dB and an input 1 dB compression point (IP1dB) of −12 dBm.

A 39 GHz broadband high-isolation CMOS mixer using magnetic-coupling CG Gm stage for 5G applications

This paper presents a 39 GHz broadband high-isolation mixer for 5G applications in 65 nm CMOS process. By adopting a common-gate (CG) gm stage with magnetic coupling, the mixer obtains a wide RF bandwidth without extra input matching components, which is benefit for system-level design. Meanwhile, it can improve gain and noise performance. Besides, a fully symmetrical design method is employed to keep a minimum LO leakage. According to experimental results, the mixer operates from 27.6 to 57.8 GHz and achieves a gain of 7.3 dB under LO power of 0 dBm. The LO-RF and LO-IF isolations are 59.5 and 57 dB, respectively.

A 27.9–53.5-GHz transformer-based injection-locked frequency divider with 62.9% locking range

An ultra-wide locking range transformer-based injection-locked frequency divider (ILFD) is presented. By making use of a 4th-order transformer-based resonator and an inductive gain peaking technique, the proposed ILFD can achieve high performance in terms of wide locking range and low power consumption. Fabricated in a standard 65nm CMOS process with a core area of 0.18mm2, the ILFD measures a locking range of 62.9% from 27.9 to 53.5 GHz while consuming 5.8mW from a 1V power supply. Moreover, when operating at 0.8V power supply, the proposed ILFD consumes only 3.2mW with 48.9% locking range.

45-GHz and 60-GHz 90 nm CMOS power amplifiers with a fully symmetrical 8-way transformer power combiner

In this paper, 45 GHz and 60 GHz power amplifiers (PAs) with high output power have been successfully designed by using 90 nm CMOS process. The 45 GHz (60 GHz) PA consists of two (four) differential stages. The sizes of transistors have been designed in an appropriate way so as to trade-off gain, efficiency and stability. Due to limited supply voltage and low breakdown voltage of CMOS MOSFET compared with the traditional III-V technologies, the technique of power combining has been applied to achieve a high output power. In particular, a novel 8-way distributed active transformer power combiner has been proposed for realizing such mm-wave PA. The proposed transformer combiner with a fully symmetrical layout can improve its input impedance balance at mm-wave frequency regime significantly. Taking its advantages of this novel transformer based power combiner, our realized 45 GHz (60 GHz) mm-wave PA has achieved the gain of 20.3 dB (16.8 dB), the maximum PAE of 14.5% (13.4%) and the saturated output power of 21 dBm (21 dBm) with the 1.2 V supply voltage.

A wideband high efficiency V-band 65 nm CMOS power amplifier with neutralization and harmonic controlling

Awideband high-efficiency V-band CMOS power amplifier (PA) is proposed in this paper. Neutralization technique is used to reduce the Miller effect and improve the power gain. A wideband on-chip transformer is used to adjust the transistors’ voltage waveform to improve the PAE performance. The PA works from 51GHz to 64GHz with 13GHz absolute bandwidth and 22.6% relative bandwidth. The output power reaches 14.9 dBm with 16.3% peak PAE. The circuit is designed in a 65 nm CMOS technology.