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Dive into the research topics where Kai Kang is active.

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Featured researches published by Kai Kang.


IEEE Journal of Solid-state Circuits | 2010

A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS

Kai Kang; Fujiang Lin; Duy-Dong Pham; James Brinkhoff; Chun-Huat Heng; Yong-Xin Guo; Xiaojun Yuan

A low power 60-GHz on-off-keying (OOK) receiver has been implemented in a commercial 90 nm RF CMOS process. By employing a novel on-chip antenna together with architecture optimization, the receiver achieves a sensitivity of -47 dBm at a bit-error rate (BER) of less than 10-3. Using a commercial transmitter with transmit power of 1.5 dBm, a transmission distance of 5 cm can be achieved at 1.2 Gbps data rate. In this design, the on-chip antenna minimizes the packaging loss, while energy detection at RF allows architecture simplification. Both techniques contribute to the receivers low power consumption of 51 mW, excluding test buffers. This leads to a bit energy efficiency of 28 pj/bit at 1.8 Gbps. The total die area is 3.8 mm2 with the on-chip antenna occupying almost half of it.


IEEE Transactions on Microwave Theory and Techniques | 2008

Scalable Transmission Line and Inductor Models for CMOS Millimeter-Wave Design

James Brinkhoff; Kok Siang Steve Koh; Kai Kang; Fujiang Lin

A new equivalent-circuit model for transmission lines and inductors on silicon is proposed. The SPICE-compatible model is suitable for time-domain simulators. It is able to fit the frequency-dependent behavior of the RLGC parameters well into the millimeter-wave range. The model is extracted from electromagnetic simulations with a simple analytic procedure with no need for tuning or optimization. A method for making the model scalable with both line length and width (or inductor diameter) is proposed. Based on this new model, a scalable measurement deembedding methodology is proposed, that can greatly reduce wafer area needed for test and deembedding structures. The fully scalable model results are compared with measurements of devices fabricated in a 90 nm CMOS process.


IEEE Transactions on Biomedical Engineering | 2012

An Inductively Powered Implantable Blood Flow Sensor Microsystem for Vascular Grafts

Jia Hao Cheong; Simon Sheung Yan Ng; Xin Liu; Rui-Feng Xue; Huey Jen Lim; Pradeep Basappa Khannur; Kok Lim Chan; Andreas Astuti Lee; Kai Kang; Li Shiah Lim; Cairan He; Pushpapraj Singh; Woo-Tae Park; Minkyu Je

Monitoring blood flow rate inside prosthetic vascular grafts enables an early detection of the graft degradation, followed by the timely intervention and prevention of the graft failure. This paper presents an inductively powered implantable blood flow sensor microsystem with bidirectional telemetry. The microsystem integrates silicon nanowire (SiNW) sensors with tunable piezoresistivity, an ultralow-power application-specific integrated circuit (ASIC), and two miniature coils that are coupled with a larger coil in an external monitoring unit to form a passive wireless link. Operating at 13.56-MHz carrier frequency, the implantable microsystem receives power and command from the external unit and backscatters digitized sensor readout through the coupling coils. The ASIC fabricated in 0.18-μm CMOS process occupies an active area of 1.5 × 1.78xa0mm


IEEE Electron Device Letters | 2010

Millimeter-Wave Passives in 45-nm Digital CMOS

Jinglin Shi; Kai Kang; Yong Zhong Xiong; James Brinkhoff; Fujiang Lin; Xiaojun Yuan

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IEEE Transactions on Advanced Packaging | 2010

On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements

Kai Kang; James Brinkhoff; Jinglin Shi; Fujiang Lin

and consumes 21.6 μW only. The sensors based on the SiNW and diaphragm structure provide a gauge factor higher than 300 when a small negative tuning voltage (−0.5–0xa0V) is applied. The measured performance of the pressure sensor and ASIC has demonstrated 0.176 mmHg/√Hz sensing resolution.


IEEE Transactions on Microwave Theory and Techniques | 2010

A New Six-Port Transformer Modeling Methodology Applied to 10-dBm 60-GHz CMOS ASK Modulator Designs

James Brinkhoff; Duy-Dong Pham; Kai Kang; Fujiang Lin

With dramatically increased ft and fmax, CMOS technologies have been widely applied in the design of millimeterwave circuits. To reduce the fabrication cost, digital CMOS processes may be used. Due to the lack of thick top metal and the reduced distance between the top metal and silicon substrates in a digital CMOS, the design of high-performance passives becomes very challenging, particularly in the millimeter-wave frequency regime. In this letter, passives with novel structures were fabricated in a 45-nm digital CMOS process. These passives, including transmission lines, spiral inductors, and metal-oxide-metal (MOM) capacitors, were designed and characterized up to 110 GHz. Their performance was compared with those fabricated using 180- and 90-nm RF CMOS processes. These passives achieved good performance in the millimeter-wave regime. A MOM capacitor has a self-resonant frequency higher than 110 GHz. An inductor achieves a quality factor of 24 at 70 GHz. These results show the feasibility of implementing the millimeterwave passives and systems in a 45-nm digital CMOS process.


IEEE Transactions on Microwave Theory and Techniques | 2011

Integration of SiP-Based 60-GHz 4

Muhammad Faeyz Karim; Yong-Xin Guo; Mei Sun; James Brinkhoff; Ling Chuen Ong; Kai Kang; Fujiang Lin

Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ¿m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz.


asian solid state circuits conference | 2009

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Fujiang Lin; James Brinkhoff; Kai Kang; Duy Dong Pham; Xiaojun Yuan

This paper presents a new broadband equivalent-circuit model for millimeter-wave transformers on silicon. The model includes a center tap on the primary and secondary, and considers coupling between all segments of the windings. A corresponding methodology to analytically extract the model from electromagnetic (EM) simulations is developed. The broadband model is verified by EM simulations and measurements. Two amplitude modulatable power oscillators with high power efficiency are demonstrated using low-loss transformers. One achieves an output power of 10.4 dBm near 57 GHz with a total efficiency of 23.6%. Applying amplitude-shift keying modulation, their maximum data rate exceeds 2 Gb/s. Simulations of these circuits showed the transformer model performs well in time-domain simulations.


IEEE Electron Device Letters | 2009

4 Antenna Array With CMOS OOK Transmitter and LNA

Jinglin Shi; Yong Zhong Xiong; Kai Kang; Lan Nan; Fujiang Lin

An integrated system-in-package-based 60-GHz 4 × 4 antenna array with CMOS on-off keying (OOK) transmitter and low-noise amplifier (LNA) is investigated. The 4 × 4 circular polarized array exhibits a wide impedance bandwidth (VSWR <; 2) and 3-dB axial ratio bandwidth of over 8 GHz using a strip line sequential rotation feeding scheme. It has a beam-shaped pattern with a 3-dB beamwidth of 20° and a peak gain of 16.8 dBi. The modulators in 90-nm CMOS includes 60-GHz oscillators and switchable amplifiers to achieve the OOK modulation. The key features of the circuits are small power consumption and size. By applying a bond wire compensation scheme, the LNA and 60-GHz CMOS modulator are successfully integrated into the low-temperature co-fired ceramic package with 2-mil 500-μm-long bond wires. The measurement results for the antenna array with LNA shows a peak gain of ~ 35 dBi. The 60-GHz CMOS modulator is tested at a data rate of 2 Gb/s and the bit-error performance of the system is also demonstrated. The energy usage of 60-GHz modulator at 2 Gb/s is only 13.2 pj/bit for the modulator.


IEEE Electron Device Letters | 2010

A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna

Kai Kang; Cher Jiun Tan; James Brinkhoff; Jinglin Shi; Fujiang Lin

Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.

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Chun-Huat Heng

National University of Singapore

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Yong-Xin Guo

National University of Singapore

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