Cherrice Traver

Cell designs for self-timed FPGAs

A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.

Early evaluation for performance enhancement in phased logic

Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.

Arithmetic logic circuits using self-timed bit level dataflow and early evaluation

A logic style known as Phased Logic (PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the original clocked netlist. Simulation results for a 16/spl times/16 iterative multiplier based on a LUT4 design show a 23% speed improvement and 20% energy improvement over the clocked design. A Y=Y@1*a +b calculation using an array multiplier design shows a 15% performance decrease but is 2/spl times/ more energy efficient than the clocked counterpart.

A fine-grain Phased Logic CPU

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique known as Early Evaluation that can be used to boost performance at the cost of additional PL gates. Several different PL gate-level implementations are produced to explore different architectural tradeoffs using early evaluation. Simulations run for five benchmark programs show an average speedup of 1.48 over the clocked netlist at the cost of 17% additional PL gates.

A coarse-grain phased logic CPU

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed implementation scheme known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of PL blocks. Each PL block is composed of control logic wrapped around a collection of DFFs and LUT4s to form a multi-input/output PL gate. PL offers a speedup technique known as early evaluation that can be used to boost performance at the cost of additional logic within each block. In addition to early evaluation, this implementation uses bypass paths in the ALU for shift and logical instructions and buffering stages for increased dataflow to further improve performance. Additional speedup is gained by reordering instructions to provide more opportunity for early evaluation. Simulation results show an average speedup of 41% compared to the clocked netlist over a suite of five benchmark programs.This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18/spl mu/ and 0.13/spl mu/) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13/spl mu/ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.

Generalized Early Evaluation in Self-Timed Circuits

Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases.

A testable model for stoppable clock ASICS

A testable model for globally asynchronous ASICs is presented. These circuits operate without a global clock and are useful for pipelined or data-driven architectures. The ASIC can be partitioned into several locally clocked modules and control is distributed throughout these modules. A test methodology is presented which partitions each locally clocked module into synchronous and asynchronous components in test mode. Design for testability techniques are used to further simplify the testing process.<<ETX>>

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion

A technique for automatic insertion of slack matching buffers for performance enhancement in the asynchronous design style known as Phased Logic (PL) is described. A description of how slack matching buffers can offer throughput increases in PL circuitry is presented and is supported through the use of a simulation tool developed for modeling the timing behavior of PL circuits. A description of the architecture of the simulator and its implementation is also discussed. Based on the analysis of results provided by the simulator and the topological characteristics of a PL circuit, an algorithm for automatic slack matching buffer placement is devised. Examples of the buffer insertion technique are given and the effectiveness of the technique is evaluated through a set of experimental results.

A comparison of synchronous and asynchronous FSMD designs

This paper presents a comparison of asynchronous and synchronous standard cell implementations for finite state machine with data-path (FSMD) ASICs. The comparison is made through independent parallel designs of a 16-bit factoring ASIC. A common functional specification, standard cell library, and suite of EDA tools for layout and simulation are used to provide a common basis for comparison. To clarify design goals and provide more data for comparison each design is separately optimized for speed and for area. Timing and area information for each design is tabulated and discussed to illustrate the specific advantages and disadvantages of each approach.<<ETX>>

Analyzing and verifying locally clocked circuits with the concurrency workbench

Locally Clocked Modules (LCMs) allow asynchronous communication between synchronous computational elements. The concurrency workbench models concurrent systems in the CCS process algebra. We describe the use of the concurrency workbench to specify, simulate, and verify implementations of LCMs and discuss its application to the specification of asynchronous circuits.