Robert B. Reese

Cooperative and progressive design experience for embedded systems

This paper describes a cooperative experiential learning activity to develop embedded systems design skills. Student teams design, build, and troubleshoot a microcontroller-based project composed of common embedded systems peripherals, including input/output and electromechanical devices, industry standard communication networks, and complex digital integrated circuits. The design experience is progressive, requiring each successive subsystem to be incorporated without disturbing previously completed subsystems. Furthermore, the design experience is based on a problem-based learning approach that motivates student learning and develops skills required by the student in a future professional capacity. These skills include designing to specification, use of third-party intellectual property, teamwork, communication, and lifelong learning skills. The design experience was offered to a cohort in conjunction with lectures using active learning techniques. Course evaluations were obtained from students and external reviewers, and the results show that the course was well received and achieved its educational objectives.

Cell designs for self-timed FPGAs

A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts.

Uncle - An RTL Approach to Asynchronous Design

Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used to produce a gate-level net list of primitive logic gates and storage elements, which is then transformed into an NCL net list by the Uncle mapping flow. Performance optimizations supported by the flow are net buffering for target slew and delay balancing between latch stages. Both data-driven and control-driven (i.e. Balsa-style) schemes are supported. Transistor count, performance, and energy comparisons are made for Uncle versus Balsa-generated net lists for GCD and Viterbi decoder designs, with the Uncle designs comparing favorably in all three areas.

Early evaluation for performance enhancement in phased logic

Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.

Arithmetic logic circuits using self-timed bit level dataflow and early evaluation

A logic style known as Phased Logic (PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the original clocked netlist. Simulation results for a 16/spl times/16 iterative multiplier based on a LUT4 design show a 23% speed improvement and 20% energy improvement over the clocked design. A Y=Y@1*a +b calculation using an array multiplier design shows a 15% performance decrease but is 2/spl times/ more energy efficient than the clocked counterpart.

A fine-grain Phased Logic CPU

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique known as Early Evaluation that can be used to boost performance at the cost of additional PL gates. Several different PL gate-level implementations are produced to explore different architectural tradeoffs using early evaluation. Simulations run for five benchmark programs show an average speedup of 1.48 over the clocked netlist at the cost of 17% additional PL gates.

A coarse-grain phased logic CPU

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed implementation scheme known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of PL blocks. Each PL block is composed of control logic wrapped around a collection of DFFs and LUT4s to form a multi-input/output PL gate. PL offers a speedup technique known as early evaluation that can be used to boost performance at the cost of additional logic within each block. In addition to early evaluation, this implementation uses bypass paths in the ALU for shift and logical instructions and buffering stages for increased dataflow to further improve performance. Additional speedup is gained by reordering instructions to provide more opportunity for early evaluation. Simulation results show an average speedup of 41% compared to the clocked netlist over a suite of five benchmark programs.This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18/spl mu/ and 0.13/spl mu/) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13/spl mu/ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.

Generalized Early Evaluation in Self-Timed Circuits

Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have been applied to asynchronous circuits in the past in order to achieve throughput increases. A general method for computing early evaluation functions is presented for this design style. Experimental results are given that show the increase in throughput of various benchmark circuits. The results show that as much as a 30% speedup can be achieved in some cases.

OpenDesign: an open user-configurable project environment for collaborative design and execution on the Internet

OpenDesign is an open user-configurable project environment that supports distributed collaborative design and execution on the Internet. The environment is created by configuring a generic client for a specific project. This is in contrast to an implementation of a project-specific client-server architecture. This paper introduces the OpenDesign environment in the contest of a design process and project-specific tasks. An OpenDesign task is defined as execution of one or more CAD point tools, whereas a task flow is a dependency graph of tasks and/or other task flows. Challenges arise when, within a single project, (1) tasks must be executed on remote hosts under different file systems, (2) data must be accessed, moved, modified, and archived with consistency, (3) tasks and task flows are assigned to more than one designer, and (4) designers are physically dispersed. In collaboration with peer institutions, a number of demo design projects demonstrate the features and the opportunities with the OpenDesign environment.

Improving the effectiveness of microcontroller education

The increased power and functionality of modern microcontrollers provides both an opportunity and a challenge to educators. Increased complexity, the necessity of integrating a hands-on lab experience, and downward pressure on total curriculum hours demand a significant investment of time to modernize microcontroller education, which few educators can afford. However, a successful microcontrollers course provides a unique opportunity to equip students to produce large, complex systems in their capstone design course. This paper details the evolution of an approach which provides an integrated course and laboratory experience for students. Results of these changes produced quantitative differences in the resulting capstone design courses, validating the approach.