Chi Chang

Corner-field induced drain leakage in thin oxide MOSFETs

A new type of leakage current between drain and substrate (n-well) in thin oxide (120A-285A) n- and p-channel MOSFETs fabricated with standard CMOS n-well process is investigated. Experimental results indicate that the origin of this leakage is due to band-to-band tunneling occurring at the deep-depleted drain junction corner. It is shown that the tunnelingI-Vbehavior can be adequately described by the analytical expression ofJ = B_{1}E_{si} \exp (-B_{2}/E_{si}). The critical drain voltage corresponding to the onset of tunneling is empirically found to be 1.3 V higher in p-channel than in n-channel. Device structures with graded junctions, such as double-diffused and LDD, are also studied and demonstrated to be effective in suppressing this leakage current.

Flash EPROM endurance simulation using physics-based models

A novel unified field-dependent oxide charge generation (FDG) model is introduced to consistently simulate oxide degradation due to Fowler Nordheim (FN) tunneling and hot carrier injection (HCI) stresses over a wide range of oxide field intensity. This model, combined with an interface charge generation model, is used to study effects of stress-induced interface and oxide charges on flash device erase and programming speeds, band-to-band tunneling leakage current, and threshold voltage shift. An efficient cycle-weighting method is introduced to simulate flash device programming/erase (P/E) cycle endurance. Excellent agreement has been achieved between the simulation predications and experimental data over various operation conditions without parameter fittings or preassumed interface and oxide charge distributions. Simulation results show that the endurance characteristics are mainly affected by both the P/E gate current reduction due to oxide charges and the flat-band voltage increase due to both oxide and interface charges.<<ETX>>

Short channel enhanced degradation during discharge of flash EEPROM memory cell

A new mode of channel length dependent degradation due to band-to-band tunneling current during the discharge of short channel flash memory device is discussed. The degradation is due to the holes created by band-to-band tunneling current and accelerated by the lateral electric field. The holes gain enough energy, are injected into the oxide and cause damage. The amount of degradation increases significantly as channel length decreases. This could be a fundamental limitation to the scaling of flash memory cells. A new discharge method is proposed to inhibit the hot hole injection and to obtain precise discharged Vt control.

Different dependence of band-to-band and Fowler-Nordheim tunneling on source doping concentration of an n-MOSFET

As the value of the maximum source doping concentration in the gate/source overlap area of an n-channel MOSFET (N/sub dmax/) varies, it has been observed that the edge Fowler-Nordheim (FN) tunneling through the gate oxide in the overlap area is changed significantly. In contrast, the N/sub dmax/ variation has little impact on band-to-band tunneling current (I/sub BB/) induced in the same overlap area. We attribute the independence of I/sub BB/ on N/sub dmax/ to the inhibition of band-to-band tunneling at the N/sub dmax/ location where silicon band bending becomes less than 1.1 eV resulting from increase of source doping concentration N/sub d/ beyond /spl sim/1.6/spl times/10/sup 19/ cm/sup -3/ (this value depends on the device used and its bias condition).

Plasma-induced in-line charging and damage in non-volatile memory devices

Plasma-induced charging in oxide/nitride/oxide (ONO) inter-dielectrics and stress damage to tunnel oxides were extensively investigated on flash memory devices. Experimental data indicated that plasma-induced in-line charging in the ONO dielectric film and tunnel oxide damage were the two mechanisms responsible for UV threshold voltage fluctuation and transconductance degradation in non-volatile memories. The degree of plasma charging in ONO dielectric and tunnel oxide increases with increasing device antenna ratios. In this paper, a physical model was successfully developed and used in explaining the observed UV threshold voltage and transconductance dependencies on device antenna ratio and stress condition. A technique of utilizing a P/sup +/-diode structure to provide effective protection against plasma-induced ONO charging and tunnel oxide stress was also demonstrated on flash memories.<<ETX>>

New erase scheme suitable for low power flash memory application

A novel erasing method utilizing avalanche hot-electron injection for low power flash memory applications is proposed and investigated. In this new bias scheme, a single internally pumped voltage (<10 V) uniformly charges up an array of cells in 0.5 sec at a current level less than 1 nA per cell. The array exhibited minimal degradation after cycling to beyond 100 K. In addition to providing superior flash reliability, this new bias scheme is suitable for low power application.