Sameer Haddad

Non-volatile resistive switching for advanced memory applications

A non-volatile resistive switching mechanism based on trap-related space-charge-limited-conduction (SCLC) is proposed. Excellent memory characteristics have been demonstrated using near-stoichiometric cuprous oxide (CuxO) metal-insulator-metal (MIM) structures: low-power operation, fast switching speed, superior temperature characteristics, and long retention. This MIM memory cell is fully compatible with standard CMOS process. The proposed switching mechanism is a strong contender for high density and low cost memory applications

Switching characteristics of Cu2O metal-insulator-metal resistive memory

The Cu2O metal-insulator-metal (MIM) resistive switching memory was characterized on a 64kb memory test array. The switching properties are consistent with the proposed switching model of conductivity modulation by a charge trapping process. Retention, programing characteristics, and temperature effects are analyzed based on the switching model. The measured characteristics and the switching model for Cu2O MIM are compared with those of other resistive switching materials. The statistical characteristics provide essential evidence for analysis of the switching mechanism and evaluation of the memory devices.

Erasing characteristics of Cu2O metal-insulator-metal resistive switching memory

The erasing characteristics of Cu2O metal-insulator-metal resistive switching memory were measured on a 64Kb memory test array. The erasing yield reaches the maximum at an optimal erasing voltage. Effective erasing requires a threshold current compliance that is higher for shorter pulse width. The erasing current and erasing power both depend strongly on the on-state before erasing, while the erasing voltage is essentially unaffected. Erasing appears to be a power-driven process, which may be related to the thermal effect of power dissipation. The experimental data and analysis suggest that erasing can be explained by field-assisted thermal emission of trapped charges.

Erase Mechanism for Copper Oxide Resistive Switching Memory Cells with Nickel Electrode

A metal-insulator-metal (MIM) device based on a Cu2O insulator has electrical characteristics significantly dependent on the oxide to top electrode (TE) interface. Cu/Cu2O/TE devices with various top electrodes have different thermal release characteristics, related to trap depth. The behavior of the device during erase with Ni and Ti top electrodes suggests different mechanisms. This paper focuses on Cu/Cu2O/Ni devices and proposes a thermal erase model, based on power calculations and temperature dependence

A Temperature-Accelerated Method to Evaluate Data Retention of Resistive Switching Nonvolatile Memory

A switching model of conductivity modulation by a charge trapping process is proposed to describe the resistive switching in nonvolatile metal-insulator-metal (MIM) memory. Based on a quantitative detrapping analysis, retention is explained by the thermal release time of trapped charges, which is determined by trap depth and temperature. A characteristic temperature is defined at which a significant loss of retention would occur. A temperature-accelerated test is devised to measure the characteristic temperature and to give an early input on the worst-case retention for a given technology. The viability of this method is demonstrated using MIM memory.

Advancement in Charge-Trap Flash memory technology

Charge-trap Flash memory has been successfully productized in high volume for several technology generations. Two-bits-per-cell MirrorBit® charge-trap technology has been the industry benchmark for NOR Flash for more than a decade, spanning six generations of scaling. More recently Heterogeneous Charge Trap (HCT)™ NAND Flash as well as embedded Charge Trap (eCT)™ NOR Flash have been developed. The planar cell structures will enable continued scaling of these charge-trap technologies, while new architectures such as 3D charge-trap Flash will emerge and further extend the density-growth trend.

Highly scalable and manufacturable heterogeneous charge trap NAND technology

For the first time, we will present production-ready heterogeneous charge trap NAND technology based on Silicon Rich Nitride. The competitive product performance, reliability, and manufacturability demonstrated at the 43nm node, in conjunction with the planar cell architecture have laid the foundation for scaling to <; 20nm.