Chi-Fang Li

ASIC design for cell search in 3GPP W-CDMA

This paper deals with an ASIC design and realization for a pipelined cell search algorithm in the 3GPP W-CDMA system. Pipelining three stages of cell search provides preferable performance, but also results in greed for high computing power. The ASIC implementation furnishes this computing power demand with a high-performance, cost-effective, and low-power solution. In the ASIC design, two synchronization code matched correlators are well designed and realized with reduced computing power. A weighted comma-free Reed-Solomon decoder is also proposed with superior performance, and realized in a cost-effective and low-power architecture. Finally, the cell search chip is designed in a 3.3-V 0.35-/spl mu/m CMOS technology with 4/spl times/4-mm/sup 2/ core area and 1.32 W power dissipation, complying with the 3GPP W-CDMA system specifications.

A low-power ASIC design for cell search in the W-CDMA system

This paper presents a low-power ASIC design for cell search in the wideband code-division multiple-access (W-CDMA) system. A low-complexity algorithm that is able to work satisfactorily under the effect of large frequency and clock errors is designed first. Then, a set of low-power measures are employed in the design of hardware architecture and circuits. Finally, through power analysis, critical blocks are identified and redesigned so as to further reduce the power consumption. The final design shows that the power is reduced by 51% from the original design of 133.6 mW to 65.49 mW, and its core area is also reduced by 31.9% from 3.4/spl times/3.4 mm/sup 2/ to 2.8/spl times/2.8 mm/sup 2/. The design is implemented and verified in a 3.3-V 0.35-/spl mu/m CMOS technology with clock rate 15.36 MHz.

An integrated multi-scheme cell search platform for W-CDMA applications

This paper proposes a cell search platform that integrates multiple schemes used for different search modes in the W-CDMA systems. There are plenty of search schemes, including frequency offset compensation, partial symbol de-spreading, multiple timing candidates, random sampling, sample point reordering, serial and pipelined searches, involved in the platform. Their computing complexities, power consumptions, and search performances are all illustrated and compared in detail. An exemplified cell search platform, which integrates all these schemes, is demonstrated to trade off performance, complexity, and power consumption in the W-CDMA systems.

A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture

This brief proposes a fast multispeed comma-free Reed-Solomon (CFRS) decoder for the frame synchronization and code-group identification in the cell search of the Third Generation Partnership Project wide-band code-division multiple access/frequency division duplexing (W-CDMA/FDD) system. A foldable systolic array is proposed to achieve fast decoding and provide flexible tradeoffs between power consumption, chip size, and decoding latency. Multispeed decoding, an idea that is useful for cell search in different application scenarios, can also be achieved with the same array architecture. The proposed CFRS decoder is implemented in a 3.3-V 0.35-/spl mu/m CMOS technology with 2.2 /spl times/ 2.2 mm/sup 2/ core area and power dissipation of 13.3 and 1.23 mW in high- and low-speed decoding modes, respectively.

Low-power design for cell search in W-CDMA

This paper presents a low-power design for cell search in the wideband code-division multiple-access (W-CDMA) system. A low-complexity algorithm is designed to work satisfactorily under large frequency and clock errors. Then, signal bit-widths within the cell search are determined to achieve good performance using as few bits as possible. Furthermore, a set of low-power measures is employed in the design of hardware architecture and circuits. Critical blocks on power consumption are further identified and redesigned to reduce power. The final design consumes only half the power of the original one.

A comma-free Reed-Solomon decoder chip for W-CDMA/FDD applications

A (15, 3) CFRS (comma-free Reed-Solomon) code has been devised in the 3GPP W-CDMA/FDD system (3/sup rd/ generation partnership project, wideband code division multiple access/frequency division duplexing) in order to facilitate frame synchronization and code-group identification in the cell search procedure. This paper proposes a CFRS decoder chip for fast, multi-speed decoding in this application. With this fast decoder, realization of more sophisticated cell search algorithms that may be needed in some application scenarios will become feasible. Besides, a multi-speed decoding can be implemented within the same architecture. Multi-speed decoding equips a mobile for being able to use different algorithms in different cell search scenarios. The decoder achieves low power dissipation with low clock rate as well as fast decoding for a cordless mobile by using a folding systolic architecture. Finally, the proposed CFRS decoder is realized in a 3.3-V 0.35-/spl mu/m CMOS technology with 2.2/spl times/2.2-mm/sup 2/ core area and 13.3/1.23-mW power dissipation.

Configurable preamble synchronizer for slotted random access in W-CDMA applications

This paper proposes a configurable preamble synchronizer based on a generic correlating-element (CE) array for slotted random access in the 3GPP W-CDMA/FDD (3/sup rd/ generation partnership project, wideband code division multiple access) system. In random access, a preamble part is usually devised for fast and reliable burst synchronization, which is essential in order to avoid excessive access delay and/or repeated transmissions. A configurable preamble synchronizer to achieve fast and reliable burst synchronization with flexible complexity/performance tradeoffs is proposed and implemented into a real ASIC based on a generic CE array and its peripheral circuits. The chip can be easily configured as active correlators (AC) or matched filters (MF) with programmable numbers of CEs and correlation lengths, etc. Finally, the proposed preamble synchronizer is realized in a 3.3-V 0.35-/spl mu/m CMOS technology with core area 7.4/spl times/7.4 mm/sup 2/ and power dissipation 483.5/600 mW in MF/AC mode operating at 15.36 MHz.