Yuan-Sun Chu

Energy Residue Aware (ERA) Clustering Algorithm for Leach-based Wireless Sensor Networks

Many energy efficient routing protocols have been proposed in sensor networks for different scenarios and various applications in literature. One of the efficient way is to group sensors in the neighboring into clusters and send aggregate data by a designated cluster head. However, such design discipline still can not balance the energy consumption of the entire network. As such, in worst cases, some nodes may be soon exhausted. Consequently, it is difficult to provide effective operation and seamless coverage in such a network. In this paper, we propose a novel clustering associating algorithm, known as Energy Residue Aware (ERA) clustering algorithm, to prolong the lifetime of a sensor network by balancing the energy consumption of the entire network. ERA enables each sensor to associate its cluster head to find a path with maximum energy residue sum instead of a path with the minimum energy consumption. Simulations are conducted to evaluate the performance in terms of the network lifetime and energy distribution among nodes. Numerical results show that proposed ERA can maintain a balanced energy consumption distribution among nodes in a sensor network and thus prolong the network lifetime.

A remote thin client system for real time multimedia streaming over VNC

This paper proposes a remote thin client system for real time multimedia streaming over VNC. A remote frame can be split as two parts, i.e. high motion part and low motion part, and transmitted through the Internet from servers to clients according to the proposed hybrid RTP protocol. A Dynamic Image Detection Scheme (DIDS) is proposed to automatically detecting the high motion part of a frame with only 1% of extra CPU loading. In addition, an Error Detection Scheme (EDS) and a Dynamic Bit-rate Control Scheme (DBCS) are also proposed to ensure good video streaming quality under bandwidth limited applications. This paper also proposes a linear time BU-level rate control algorithm to ensure the proposed DBCS can be finished in real time. The proposed algorithm reduces the computational complexity from O(n2)to be O(n). By using the proposed thin client system, we can achieve about 22 fps of real-time SIF video streaming with good video quality under 32 KByte/s of bandwidth limitation, which speeds up about 172 times in remote frame display when compared to pure VNC.

Review: H.264 video transmissions over wireless networks: Challenges and solutions

Multimedia video streaming is becoming increasingly popular. Using multimedia services, there are more and more users in end-system over wireless networking environment. H.264/AVC is now the standard for video streaming because of its high compression efficiency, robustness against errors and network-friendly features. However, providing the desired quality of service or improving the transmission efficiency for H.264 video transmissions over wireless networks present numbers of challenges. In this paper, we consider those challenges and survey existing mechanisms based on the protocol layers they work on. Finally, we address some open research issues concerning for H.264 video transmission in wireless networks.

A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique

This paper presents a versatile multimedia functional unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the spurious power suppression technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18 mum/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.

A high-performance low power direct 2-D transform coding IP design for MPEG-4 AVC/H.264 with a switching power suppression technique

This paper proposes a high-performance low-power direct 2-D transform coding IP design for H.264 with a switching power suppression technique. The proposed transform coding design not only suitably arranges the data sequences in row and column transforms to greatly increase the data processing rate but also takes advantage of the correlation existed in natural video sequences to suppress the spurious switching power. When compared with the parallel transform architecture (Wang, et al., 2003), this design possesses 4 times higher data processing rate (in terms of pixels/cycle) and 3.52 times higher throughput (in terms of pixels/sec) at the cost of 1.80 times hardware cost in computing the multi-transform for H.264. In addition, without voltage scaling, the power consumed by the proposed forward transform design is only 35% of that consumed by the forward transform design in (Wang, et al., 2003) to maintain the same throughput. When the proposed switching power suppression technique is applied, the proposed transform design can perform digital cinema video coding format by consuming only 1.86 mW.

A high-throughput and high-capacity IPv6 routing lookup system

With the growing number of routing entries, IP routing lookup has become the major performance bottleneck in backbone routers. In this paper, a complete hardware-based routing lookup system is proposed to achieve high-throughput and high-capacity for IPv6. The proposed system is a cache-centric, hash-based architecture that contains a routing lookup application specific integrated circuit (ASIC) and a memory set. A hash function is used to reduce lookup time for the routing table and ternary content addressable memory (TCAM) effectively resolves the collision problem. The gate count of the ASIC, excluding the binary content addressable memory (BCAM), is about 5306 gates, using an in-house 0.18@mm CMOS single-poly six-metal standard cell library. The results of post-layout simulations show that the ASIC operates in 3.6ns so that the routing lookup system approaches 260 Mega lookups per second (Mlps), which is sufficient for 100Gbps networks. The memory density is good, with each routing entry requiring only 64bits. Moreover, the routing table only needs 10.24KB on-chip BCAM, 20.04KB off-chip TCAM and 29.29MB DRAM for 3.6M routing entries in the proposed system.

An Area-Efficient Variable Length Decoder IP Core Design for MPEG-

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-1/2/4 video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-1/2/4 entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage while maintaining enough data throughput rate. Moreover, we propose a partial combinational component enabling approach for minimizing the power consumption of the proposed design. Based on 0.18-mum CMOS technology, the implementation results show that the proposed IP core operates at 125-MHz clock frequency with the cost of 13 105 gates. In addition, the power consumption of the proposed design reaches 163.4 muW operated at 12.5 MHz with 0.9-V supply voltage, which is fast enough for MPEG-1/2/4 real-time decoding on 4CIF video@30 Hz. Compared to the existing designs, the proposed IP core possesses both higher data throughput and less hardware cost

hbox 1/2/4

This paper presents the design exploration and applications of a spurious-power suppression technique (SPST) which can dramatically reduce the power dissipation of combinational VLSI designs for multimedia/DSP purposes. The proposed SPST separates the target designs into two parts, i.e., the most significant part and least significant part (MSP and LSP), and turns off the MSP when it does not affect the computation results to save power. Furthermore, this paper proposes an original glitch-diminishing technique to filter out useless switching power by asserting the data signals after the data transient period. This paper adopts two multimedia/DSP design examples, i.e., a multitransform design for H.264 and a versatile multimedia functional unit (VMFU), to evaluate the proposed SPST. These two design examples have quite different hardware configurations, thus, the realization issues of the SPST on every design also remarkably differ from each other. The multitransform design can compute three transforms which are required in H.264 encoding while the VMFU possesses six commonly used multimedia/DSP functions, namely, addition, subtraction, multiplication, MAC, interpolation, and sum-of-absolute-difference. After optimizing the design elaborately, we find that the proposed SPST can, respectively, save 27% and 24% power dissipation on average of the H.264 multitransform design and the VMFU at the expense of less than 20% area augmentation.

Video Coding Applications

This paper proposes an efficient Spurious Power Suppression Technique (SPST) and its applications on an MPEG-4 AVC/H.264 transform coding design. There are three techniques addressed in this paper, which are (1) the SPST, (2) the direct 2-D algorithm, and (3) the interlaced I/O schedule to solve the design challenges induced by both the real-time processing and low-power requirements. The major novelty of this paper is implementing the SPST concept on the transform architecture for H.264, which save 31.9% power consumption at the cost of 20.9% area price. Moreover, the proposed transform design also possesses 60.05% higher hardware efficiency through the TPUA index than the existing designs

A Spurious-Power Suppression Technique for Multimedia/DSP Applications

Unlike the channel matrix in the spatial division multiplexing (SDM) multiple-input multiple-output (MIMO) communication system, the equivalent channel matrix in the layered Alamouti space-time block coding (STBC) MIMO system comprised 2-by-2 Alamouti sub-blocks. One novel property, found by Sayed about the QR-decomposition (QRD) of this equivalent channel matrix is that the produced Q- and R-matrices are also matrices with Alamouti sub-blocks. Taking advantage of this property, we propose a new block-wise complex Givens rotation (BCGR) based algorithm and a triangular systolic array (TSA) to compute the QRD of the equivalent channel matrix in an Alamouti block by block manner. Implementation results reveal that our new TSA can compute QRDs of 4-by-4 equivalent channel matrices faster than any architecture that has been developed for the SDM MIMO system. This property of fast QRD makes our TSA very attractive for the layered Alamouti STBC MIMO system combined with the orthogonal frequency division multiplexing. Our new BCGR based approach can also be applied to the hybrid Alamouti STBC MIMO system, which is also a system with equivalent channel matrix consisting of Alamouti sub-blocks.