Chi-Sheng Lin

A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process

Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is presented, where the supply voltage of 1.0 V is employed. The divider achieves a full modulus range from 1 to 256 and operates over a wide range maintaining up to 4 GHz with -30-dBm input power. The divider also accomplishes a power efficiency of 12.8 GHz/mW with 0.5-V supply voltage. It is favorable for advanced processes.

High-speed and low-power programmable frequency divider

This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using the TSMC 0.18 μm 1P6M CMOS process. With an 8-stage 2/3 divider cell, the measurement results indicate that the proposed circuit operates up to 5.8GHz with the power-consumption less than 3.24mW.

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with plusmn2 N-1 times 2pi linear range with N-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 mus logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is -48.7 dBc and the phase noise is -88.31dBc/Hz at 10 kHz offset with KVCO = - 2 GHz/V.

An edge-missing compensator for fast-settling wide-locking-range PLLs

An ideal phase detector (PD) produces an output signal whose DC value is linearly proportional to the phase difference (??) between the phases of its two periodic inputs. In practice, however, the transfer curve of the PD may not be linear or even monotonic for large ??. With a nonlinear PD, the transient response of PLL cannot be easily formulated and slow down the acquisition behavior [1].

An effective phase detector for phase-locked loops with wide capture range and fast acquisition time

This paper describes and resolves the false locking issue in phase-locked loops (PLLs) with π-phase detector. In order to verify the proposed approach for acquisition and capture range performances of π-phase detector, the phase-controlled-current-source (PCCS) using the reversing scheme is implemented in TSMC 0.18um 1P6M CMOS technology. In the simulation results, the locking time of the proposed approach is 6.7X faster than conventional PFD design. Moreover, the measurement results indicate the locking time of testing PLL is less than 2us.

A high sensitivity, low power Phase Controlled Current Source for Gsamples/s phase-locked loops

Operating up to 3.2-GHz with power consumption of 1.32mW, a Phase Controlled Current Source (PCCS) capable of both phase frequency comparing and current providing is presented. Benefiting from simple, feed-forward operation characteristic, the PCCS minimizes the short current issue while maintaining free dead zone feature. The phase and frequency sensitivities of the PCCS have been measured to demonstrate its performance. With a reference source ranging from 2.1-GHz to 3.2-GHz, a PLL embedding the PCCS achieves phase noise around −100 dBc/Hz at 1-kHz offset. The lowest phase noise at 1MHz offset is −131 dBc/Hz when the PLL uses a 2.3-GHz reference source.

A Forward Phase Detector for GSamples/s Phase-Locked Loops

The PLL implementing with the conventional Phase/ Frequency Detector (C-PFD) with feedback-path approach suffers from a dead-zone problem is generally resulted in slow acquisition time. A reasonably wider concurrent pulse is required to achieve a dead-zone free detection. The wider concurrent pulse implies the slow acquisition time PLL. This study presents a novel forward Phase Detector (fPD). The dead-zone-free fPD is operated in two modes: ON (M=1) and OFF (M=0). Both input signals INT and EXT are fed into both fPD and CP. The fPD determines the operation mode, while the CP performs the operation of charge/discharge. Two steady signals EXT and INT are used to replace the concurrent pulse in the feedback-path in the C-PFD. Thus, it is a “pulse-less” forward phase detecting scheme. A high-speed PLL with the proposed fPD/CP combination can be achieved. Due to the low disturbance to the Voltage Controlled Oscillator (VCO) control line, the PLL achieves a phase noise of -131 dBc/Hz at 1 MHz offset when the PLL is operated at 2.3 GHz. The low power fPD/CP also achieves high sensitivity for detecting both frequency and phase.