Chin-Long Wey

Built-in self-test (BIST) structure for analog circuit fault diagnosis

An analog built-in self-test (BIST) structure for analog circuit fault diagnosis is described that increases the numbers of test points while still keeping low pin overhead. The BIST structure allows access to some internal nodes so that the fault diagnosis process can be significantly simplified. The BIST structure also allows designers to use one channel of an oscilloscope to simultaneously monitor multiple output waveforms of analog circuits or systems. >

On the Repair of Redundant RAM's

This paper describes a set of novel conditions that can be integrated in a computer-aided-testing (CAT) package for repair of redundant RAMs. A new approach is proposed; the innovative feature of this approach is the independence of analysis on the distribution of faulty bits in memory. This results in better exploitation of redundancy and efficient adaptability of this technique to various testing methods, such as the ones that employ region totalizers and fault counters. Algorithms that provide repair solution and earliest detection of unrepairability of a device are presented. The benefits that result by using this approach include a reduction in repair time. Conditions of unrepairability are given as a function of the number of spare resources (columns and rows) in the redundant memory; significant improvement over existing techniques is accomplished. Simulation results are provided to substantiate the validity of the proposed theory.

Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation

Given a set of numbers X, finding the minimum value of X, min_1st, is a very easy task. However, efficiently finding its second minimum value, min_2nd, requires the derivations of min_1st and finding the minimum value from the set of the remaining numbers. Efficient algorithms and cost-effective hardware of finding the two smallest of X are greatly needed for the low-density parity-check (LDPC) decoder design. The following two architectures are developed in this paper: (1) sorting-based (XS) approach and (2) tree structure (TS) approach. Experimental results show that the XS approach provides less number of comparisons, while the TS approach achieves higher speed performance at lower hardware cost. Since the hardware unit is repeatedly used in the LDPC decoder design, the proposed high-speed low-cost TS approach is strongly recommended.

Built-in self-test (BIST) structures for analog circuit fault diagnosis with current test data

In order to increase the number of test points, while still keeping low pin overhead, a built-in self-test (BIST) structure has been proposed for analog circuit fault diagnosis with voltage test data. The authors present alternative BIST structures for fault diagnosis with current test data using current copiers. The current copiers make a practically identical copy of the current without the need of well-matched components. Thus the proposed BIST structure requires less chip area. The proposed structure allows simultaneous sampling of current test data at various test points and shifting of the data to the output portion for fault diagnosis. Results have also shown that the proposed BIST structure is fully testable. >

On the implementation of an analog ATPG: the nonlinear case

A self-testing algorithm in which post-test simulation with failure bounds is employed, has been proposed. Based on this self-testing algorithm, an analog Automatic Test Program Generation (ATPG) for linear circuits or systems is being developed. The AATPG code is subdivided into off-line and on-line components while the actual test can be run in either a fully automatic mode or interactively.

Test generation and concurrent error detection in current-mode A/D converters

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques has been employed in analog-to-digital (A/D) converters to eliminate errors caused by offset and low frequency noise and cancel the error effect. For real-time applications, however, it is rather difficult to achieve validation of the converted data in the presence of faulty switching element(s). In this paper, fault behaviors and test generation of a current-mode A/D converter are addressed. Results show that the converter achieves full testability with two test currents. In addition, an A/D converter with concurrent error detection capability is proposed. The converter detects all transient faults. >

On yield consideration for the design of redundant programmable logic arrays

Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair defective chip; then the additional spare lines may increase rather than decrease the chip yields. The possibility of yield enhancement through redundant design is analyzed, showing that the chip yield is increased significantly. >

Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits

Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor techniques. A placement with higher correlation coefficients of the unit capacitors results in a higher acceptance rate, or chip yield. This paper proposes a heuristic algorithm that quickly and automatically derives the placement of the unit capacitors with the highest, or near-highest, correlation coefficients for yield improvement. Results show that the resultant placement derived from the proposed algorithm achieves better yield improvement than that from a common centroid approach. The proposed heuristic algorithm can be applied for any arbitrary capacitor ratios, i.e., more than two capacitors.

On the design of a redundant programmable logic array (RPLA)

The design is presented, in which a conventional PLA is modified by adding redundancy circuits. Three types of fault can be repaired: crosspoint, bridging, and stuck-at faults.

The design of concurrent error diagnosable systolic arrays for band matrix multiplications

The characteristics of a systolic array and the important issues in fault-tolerant systolic computing are presented. Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of systolic design in order to exemplify the extremes in design philosophies. The motivations for additional figures of merit are pointed out, and a novel BMMSA design is introduced. An efficient scheme, based on the time-redundancy technique of RESO (recomputation with shifted operands), is applied to the design of CED-capable BMMSAs. Different designs, based on the Kung-Leiserson BMMSA, the proposed BMMSA, and the Huang-Abraham BMMSA, are presented. >