Chi-Ying Tsui

A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels

Lattice decoding algorithms have been proposed for implementing the maximum likelihood detector (MLD), which is the optimal receiver for multiple-input multiple-output (MIMO) channels. However the computational complexity of direct implementation of the lattice decoding algorithm is high and the throughput is variable. In this work, a K-best algorithm is proposed to implement the lattice decoding. It is computational inexpensive and has fixed throughput. It can be easily implemented in a pipelined fashion and has similar performance as the optimal lattice decoding algorithm if high value of K is used. In this paper, we describe a pipelined VLSI architecture for the implementation of the K-best algorithm. The architecture was designed and synthesized using a 0.35 /spl mu/m library. For a 4-transmit and 4-receive antennas system using 16-QAM, a decoding throughput of 10 Mbit/s can be achieved.

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

A single-inductor multiple-output switching converter operates in pseudo-CCM/DCM. It requires freewheeling of the inductor current during the instants when the n switch and all output p switches are off. It is fabricated in a 0.5 /spl mu/m CMOS n-well process with Voa=2.5 V and Vob=3.0 V. With 1 /spl mu/H inductor, converter efficiency is 84.7% at 1 MHz.

Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode

An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-/spl mu/H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices

A low-loss CMOS full-wave active rectifier is presented. It consists of two dynamically biased and symmetrically matched active diodes each realized by an nMOS switch driven by a 2-ns voltage comparator with reverse-current control. With a load of 1.8-kOmega, the rectified dc voltage is 3.22 V and 1.2 V for a 13.56 MHz ac sinusoidal input voltage of 3.5 V and 1.5 V respectively. It is fabricated in a 0.35-mum CMOS process with an active area of 0.0055 mm 2, with no low-threshold devices and on-chip passive components

A real-time sub-carrier allocation scheme for multiple access downlink OFDM transmission

In this paper, we propose sub-carrier allocation algorithms for a multiple access scheme in downlink OFDM transmission. Knowing the channel characteristics of all the users at the base station, the sub-carrier allocation algorithm assigns sub-carriers to the users in a way that the total transmit power is minimized. An optimal algorithm is presented to provide the best sub-carrier assignment. The complexity of the optimal solution renders it impractical for real-time application. To deal with the frequently changing channel characteristic of a fast time-varying multipath fading channel, a heuristic algorithm based on constructive assignment and iterative improvement is proposed which can give out a valid solution in real time. Experimental results show that the performance of this real-time algorithm is close to that of the optimal allocation.

Technology Decomposition and Mapping Targeting Low Power Dissipation

In this paper, we address the problem of minimizing the average power dissipation during the technology dependent phase of logic synthesis. Our approach consists of two steps. In the first step, we generate a NAND decomposition of an optimized Boolean network such that the sum of average switching rates for all nodes in the network is minimum. Our power-efficient decomposition procedure is optimal for dynamic CMOS circuits with uncorrelated input signals and produces very good results for static CMOS. In the second step, we perform a power efficient technology mapping that finds an optimal power-delay trade-off value (subject to the unknown load problem) for given timing constraints. We obtain an average of 21% improvement in power at the expense of 12.6% increase in area and without any degradation in performance on a number of benchmarks.

Low power architecture design and compilation techniques for high-performance processors

Reducing switching activity would significantly reduce power consumption of a processor chip. The authors present two novel techniques, Gray code addressing and Cold scheduling, for reducing switching activity on high performance processors. They use Gray code which has only one-bit different in consecutive number for addressing. Due to locality of program execution, Gray code addressing can significantly reduce the number of bit switches. Experimental results show that for typical programs running on a RISC microprocessor, using Gray code addressing reduce the switching activity at the address lines by 30/spl sim/50% compared to using normal binary code addressing. Cold scheduling is a software method which schedules instructions in a way that switching activity is minimized. The authors carried out experiments with cold scheduling on the VLSI-BAM. Preliminary results show that switching activity in the control path is reduced by 20-30%.<<ETX>>

Low-power VLSI design for motion estimation using adaptive pixel truncation

Power consumption is very critical for portable video applications such as portable videophone and digital camcorder. Motion estimation (ME) in the video encoder requires a huge amount of computation, and hence consumes the largest portion of power. We propose a novel method of reducing power consumption of the ME by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the least significant bits of the pixel data, which is governed by the bit-rate control mechanism. Experimental results show that on average more than 4 bits ran be truncated without significantly affecting the picture quality. This results in more than 60% reduction in power consumption.

Efficient estimation of dynamic power consumption under a real delay model

In CMOS circuits, glitches account for a sizeable part of the total power consumption. In this paper, we present a fast and memory efficient power estimation technique for CMOS circuits which estimates the power consumed due to the glitches. Our technique is based on the notion of tagged transition waveforms. In particular, we approximate the correlation between transition waveforms for two signal lines by the correlation between the steady state values of these lines. We obtain an order of magnitude speed up over an exact method with an average error of only 1%.