Wing-Hung Ki

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

A single-inductor multiple-output switching converter operates in pseudo-CCM/DCM. It requires freewheeling of the inductor current during the instants when the n switch and all output p switches are off. It is fabricated in a 0.5 /spl mu/m CMOS n-well process with Voa=2.5 V and Vob=3.0 V. With 1 /spl mu/H inductor, converter efficiency is 84.7% at 1 MHz.

Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode

An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-/spl mu/H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices

A low-loss CMOS full-wave active rectifier is presented. It consists of two dynamically biased and symmetrically matched active diodes each realized by an nMOS switch driven by a 2-ns voltage comparator with reverse-current control. With a load of 1.8-kOmega, the rectified dc voltage is 3.22 V and 1.2 V for a 13.56 MHz ac sinusoidal input voltage of 3.5 V and 1.5 V respectively. It is fabricated in a 0.35-mum CMOS process with an active area of 0.0055 mm 2, with no low-threshold devices and on-chip passive components

A system-on-chip EPC Gen-2 passive UHF RFID tag with embedded temperature sensor

This paper presents a system-on-chip passive RFID tag with an embedded temperature sensor for the EPC Gen-2 protocol in the 900-MHz UHF frequency band. A dual-path clock generator is proposed to support both applications with either very accurate link frequency or very low power consumption. On-chip temperature sensing is accomplished with a time-readout scheme to reduce the power consumption. Moreover, a gain-compensation technique is proposed to reduce the temperature sensing error due to process variations by using the same bandgap reference of the tag to generate bias currents for both the current-to-digital converter and the clock generator of the sensor. Also integrated is a 128-bit one-time-programmable (OTP) memory array based on gate-oxide antifuse without extra mask steps. Fabricated in a standard 0.18- μm CMOS process with analog options, the 1.1-mm2 tag chip is bonded onto an antenna using flip-chip technology to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. The tag inlay achieves a sensitivity of -6 dBm and a sensing inaccuracy of ±0.8° C (3 σ inaccuracy) over operating temperature range from -20°C to 30°C with one-point calibration.

Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications

An integrated DC-DC hysteretic buck converter with ultrafast adaptive output transient response for reference tracking is presented. To achieve the fastest up-tracking speed, the maximum charging current control is introduced to charge up the output voltage with the maximum designed current. For down-tracking, the output is discharged by the load only to save energy. Although the converter works with hysteretic voltage mode control, an adaptive delay compensation scheme is employed to keep the switching frequency constant at 850 kHz to within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process. With an input voltage of 3 V, the output voltage can be regulated between 0.5 and 2.5 V. With a load resistor of 10 Omega, the up-tracking speed of the maximum reference step (0.5 to 2.5 V) is 12.5 mus/V. All design features are verified by extensive measurements.

Single-inductor multiple-output switching converters

A family of single-inductor multiple-output switching power converters is presented. They can be classified into same-type, bipolar and mixed-type converters. Synchronous rectification and control loop design are discussed, and experimental and simulation results of representative converters are presented to verify the functionality of these converters.

A 0.9V 0.35 μm Adaptively Biased CMOS LDO Regulator with Fast Transient Response

Portable applications often need multiple voltages controlled by a power management IC to power up many functional blocks. A switching pre-regulator is usually followed by a low dropout (LDO) regulator to provide a regulated power source for noise-sensitive blocks. The LDO regulator has to be stable for all load conditions and frequency compensation is usually needed to stabilize the regulation loop. The output voltage droop due to rapid and large load changes could be minimized with a fast regulation loop, such that functional blocks powered by the same LDO regulator would have low crosstalk noise. A low-voltage fast transient-response LDO regulator using an inexpensive 0.35 mum CMOS process is presented in this paper. It features a current-efficient adaptively biased regulation scheme using a low-voltage high-speed super current mirror and does not require a compensation capacitor. It is stabilized by a low-cost low-ESR ceramic filter capacitor of 1 muF The adaptively biased error amplifier EA drives a small transconductance cell to modulate the output current through a transient-enhanced super current-mirror (SCM).

The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control

An inductor-less on-chip micro power management system for light energy harvesting applications is presented. We target at wide variety of applications that operate at different lighting environments ranging from strong sunlight to dim indoor lighting where the output voltage from the photovoltaic cells is low. A step-up charge pump is used to directly operate the circuit or to charge a rechargeable battery. The power management system operation is discussed and the control strategy for transferring the maximum output power from the power system is presented. Low power circuit design is proposed for the implementation of the system maximum output power control. The system was implemented using a 0.35-mum CMOS process. The chip was fabricated and measurements were conducted for different lighting conditions to demonstrate the system operation and verify the control strategy.