Chi-Yuan Hung

Model-based insertion and optimization of assist features with application to contact layers

To shorten the turn around time and reduce the amount of effort for SRAF insertion and optimization on any arbitrary layout, a new model-based SRAF insertion and optimization flow is developed. It is based on the pixel-based mask optimization technique [1] to find the optimal mask shapes that result in the best image contrast. The contrast-optimized mask is decomposed into main features and assist features. The decomposed assist features are then run through a simplification process for shot count reduction to improve mask writing throughput. Model-based Optical Proximity Correction (OPC) is applied finally to achieve required pattern fidelity for the current technology. In this flow, main features and assist features are allowed to be optimized simultaneously such that the effect of SRAF optimization and Optical Proximity Correction (OPC) are achieved. Since the objective of the mask optimization is the image fidelity, and there is no light coming through assist features (in dark field case), the assist features were ensured not to print even with high dose. The results on 65nm/contact layer showed this approach greatly reduced the total time and effort required for SRAF placement optimization compared to rule-based method, with better lithographic performance for various layout types when compared to rule-based approach.

Model-based DRC for design and process integration

Accurately and efficiently verifying the device layout is a crucial step in semiconductor manufacturing. A single missed design violation carries the potential for a disastrous and avoidable yield loss. Typically, design rule checking (DRC) is accomplished by validating drawn layout geometries against pre-determined rules, the specifics of which are derived empirically or from lithographic first principles. These checks are intrinsically rigid, and, taken together, a set of DRC rules only approximate the manufacturable design space in the crudest manner. Process-specific effects are entirely neglected. But for leading-edge technologies, process variations significantly impact the manufacturability of a design, so traditional DRC becomes increasingly difficult to implement, or worse, speciously inaccurate. Fortunately, the rise of Optical Proximity Correction (OPC) has given manufacturers a means to accurately model optical and process effects, and, therefore, an opportunity to introduce this information into the layout validation flow. We demonstrate an enhanced, full-chip DRC technique, which utilizes process models to locate marginal or bad design features and classify them according to severity.

A methodology to take LER effect into OPC modeling algorithm

Model-Based OPC has become a standard practice and centerpiece for 130nm technology node and below. And every model builder is trying to setup a physically realistic model that is adequately calibrated contains the information which can be used for process predictions and analysis of a given process. But there still are some unknown/not-well-understood physics in the process such as line edge roughness (LER). The LER is one of the most worrisome non-tool-related obstacles faced by next-generation lithography. Nowadays, considerable effort is devoted to moderating its effects, as well as understanding its impact on devices. It is a persistent problem for 193 nm micro-lithography and will carry us for at least three generations, culminating with immersion lithography. Some studies showed LER has several sources and forms. It can be quantified by an LER measurement with a top-down CD measurement. However, there are other ways in which LER shows up, such as line breakage results from insufficient resist or mask patterning processes, line-width aspect ratio or just topography. Here we collected huge amount of line-width ADI CD datasets together with LER for each edge. And try to show even using the average value of different datasets will take the inaccuracy of measurement into the modeling fitting process, which makes the fitting process more time consuming and might cause losing convergence and stableness. This work is to weight different wafer data points with a weighting function. The weighting function is dependent on the LER value for each One-dimension feature in the sampling space of the modeling fitting. By this approach, we can filter wrong information of the process and make the OPC model more accurate. Further more, we will introduce this factor (LER) into variable threshold modeling parameters and see its differentiations between other Variable Threshold model forms.

A novel approach for full-chip SRAF printability check

With the critical dimension of IC design decreases dramatically, to meet the yield target of the manufacture process, resolution enhancement technologies become extremely important nowadays. For 90nm technology node and below, sub rule assistant feature (SRAF) are usually employed to enhance the robustness of the micro lithography process. SRAF is really a powerful methodology to push the process limit for given equipment conditions. However, there is also a drawback of the SRAF. It is very hard to predict the printability of the SRAFs, especially when SRAF is applied on full chips. This work is trying to demonstrate a new approach to check the printability of the SRAF on full-chip level. First, we try to capture the lithography process information through real empirical wafer data. Then we try to determine the margin of the conditions for which SRAFs can be printed out on the wafer. Based on all the information, we can then apply full chip optical rule check (ORC) to check the printability of SRAF. By this approach, the printout risk of the SRAF can be reduced effectively with acceptable time consuming.

Lithography process related OPC development and verification demonstration on a sub-90nm poly layer

Using a commercialized product Calibre OPC platform, optical and process models were built that accurately predict wafer-level phenomena for a sub-90nm poly process. The model fidelity relative to nominal wafer data demonstrates excellent result, with EPE errors in the range of ±2nm for pitch features and ±7 for line-end features. Furthermore, these models accurately predict defocus and off-dose wafer data. Overlaying SEM images with model-predicted print images for critical structures shows that the models are stable and accurate, even in areas especially prone to pinching or bridging. In addition, process window ORC is shown to identify potential failure points within some representative designs, allowing the mask preparation shop to easily identify these areas within the fractured data. And finally, the data and images of mask hotspots will be shown and compared down to wafer level.

Simulation-based scattering bar generation for 65-nm and beyond

As critical dimension decreases rapidly, scattering bars are widely implemented to increase lithographic common process window. However, collecting rules for applying scattering bar is extremely time-consuming, because of huge numbers of scattering bar split conditions should be considered. The objective of this work is to use Calibrated OPC model to simulate and insert scattering bars for hole-layers. Maximum/optimized process margin can be achieved (under fixed process condition) by calculating the EPE variation due to dose and focus variation at different sets of sub design rule assistant feature conditions, which we call pseudo process window simulation. Then one theoretically best condition for applying SRAF can be found. According this best condition, we can dramatically narrow down the search range of the SRAF rules in wafer-lever experiments. As a result, technology development cycle time can be shortened exponentially. And finally, the simulation data of our work will be shown and compared down to wafer level.

Model base SRAF insertion check with OPC verify tools

With the critical dimension of IC design decreases dramatically, to meet the yield target of the manufacture process, resolution enhancement technologies become extremely important nowadays. For 90nm technology node and below, sub rule assistant feature (SRAF) are usually employed to enhance the robustness of the micro lithography process. SRAF is really a powerful methodology to push the process limit for given equipment conditions. However, there is also a drawback of the SRAF. It is very hard to check the reasonability of the SRAF location, especially when SRAF is applied on full chips. This work is trying to demonstrate a model-based approach to do full-chip check of the SRAF insertion rule. First, we try to capture the lithography process information through real empirical wafer data. Then we try to check every SRAFs location and to find any hot spot that has the risk of being printed out on the wafer. Based on this approach, we can then not only apply full chip check to reduce the printability of SRAF. Furthermore, combined with DRC tools, we can find SRAFs that are inserted unreasonably and then apply modification on them.