Travis Brist

Source polarization and OPC effects on illumination optimization

To perform a thorough source optimization during process development is becoming more critical as we move to leading edge-technology nodes. With each new node the acceptable process margin continues to shrink as a result of lowering k1 factors. This drives the need for thorough source optimization prior to locking down a process in order to attain the maximum common depth of focus (DOF) the process will allow. Optical proximity correction (OPC) has become a process-enabling tool in lithography by providing a common process window for structures that would otherwise not have overlapping windows. But what effect does this have on the source optimization? With the introduction of immersion lithography there is yet another parameter, namely source polarization, that may need to be included in an illumination optimization process. This paper explored the effect polarization and OPC have on illumination optimization. The Calibre ILO (Illumination Optimization) tool was used to perform the illumination optimization and provided plots of DOF vs. various parametric illumination settings. This was used to screen the various illumination settings for the one with optimum process margins. The resulting illumination conditions were then implemented and analyzed at a full chip level. Based on these results, a conclusion was made on the impact source polarization and OPC would have on the illumination optimization process.

Model-based insertion and optimization of assist features with application to contact layers

To shorten the turn around time and reduce the amount of effort for SRAF insertion and optimization on any arbitrary layout, a new model-based SRAF insertion and optimization flow is developed. It is based on the pixel-based mask optimization technique [1] to find the optimal mask shapes that result in the best image contrast. The contrast-optimized mask is decomposed into main features and assist features. The decomposed assist features are then run through a simplification process for shot count reduction to improve mask writing throughput. Model-based Optical Proximity Correction (OPC) is applied finally to achieve required pattern fidelity for the current technology. In this flow, main features and assist features are allowed to be optimized simultaneously such that the effect of SRAF optimization and Optical Proximity Correction (OPC) are achieved. Since the objective of the mask optimization is the image fidelity, and there is no light coming through assist features (in dark field case), the assist features were ensured not to print even with high dose. The results on 65nm/contact layer showed this approach greatly reduced the total time and effort required for SRAF placement optimization compared to rule-based method, with better lithographic performance for various layout types when compared to rule-based approach.

Illumination optimization effects on OPC and MDP

Illumination optimization has always been an important part of the process characterization and setup for new technology nodes. As we move to the 130nm node and beyond, this phase becomes even more critical due to the limited amount of available process window and the application of advanced model based optical proximity corrections (OPC). Illumination optimization has some obvious benefits in that it maximizes process latitude and therefore makes a process more robust to dose and focus variations that naturally occur during the manufacturing process. By mitigating the effect of process excursions, there are fewer numbers of reworks, faster cycle times and ultimately higher yield. Although these are the typical benefits associated with illumination optimization, there are also other potential benefits realized from an OPC modeling and mask data preparation (MDP) perspective as well. This paper will look into the not so obvious effects illumination optimization has on OPC and MDP. A fundamental process model built with suboptimal optical settings is compared against a model based on the optimal optical conditions. The optimal optical conditions will be determined based on simulations of the process window for several structures in a design using a metric of maximum common depth of focus (DOF) for a given minimum exposure latitude (EL). The amount of OPC correction will be quantified for both models and a comparison of OPC aggressiveness will be made. OPC runtimes will also be compared as well as output file size, amount of fragmentation, and the number of shot counts required in the mask making process. In conclusion, a summary is provided highlighting where OPC and MDP can benefit from proper illumination optimization.

Impact of process variation on 65nm across-chip linewidth variation

The latest improvements in process-aware lithography modeling have resulted in improved simulation accuracy through the dose and focus process window. This coupled with the advancements in high speed, full chip grid-based simulation provide a powerful combination for accurate process window simulation. At the 65nm node, gate CD control becomes ever more critical so understanding the amount of CD variation through the full process window is crucial. This paper will use the aforementioned simulation capability to assess the impact of process variation on ACLV (Across-Chip Linewidth Variation) and critical failures at the 65nm node. The impact of focus, exposure, and misalignment errors in manufacturing is explored to quantify both CD control and catastrophic printing failure. It is shown that there is good correlation between predicted and experimental results.

Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability

Sub-resolution assist features (SRAFs) or scatter bars (SBs) have steadily proliferated through IC manufacturer data preparation flows as k1 is pushed lower with each technology node. The use of this technology is quite common for gate layer at 130 nm and below, with increasingly complex geometric rules being utilized to govern the placement of SBs in proximity to target layer features. Recently, model based approaches for placement of SBs has arisen. In this work, the variety of rule-based and model-based SB options are explored for the gate layer by using new characterization and optimization functions available in the latest generation of correction and OPC verification tools. These include the ability to quantify across chip CD control with statistics on a per gate basis. The analysis includes the effects of defocus, exposure, and misalignment, and it is shown that significant improvements to CD control through the full manufacturing variability window can be realized.

Minimizing yield-loss risks through post-OPC verification

In our continued pursuit to keep up with Moors Law we are encountering lower and lower k1 factors resulting in increased sensitivity to lithography / OPC un-friendly designs, mask rule constraints and OPC setup file errors such as bad fragmentation, sub-optimal site placement, and poor convergence during the OPC application process. While the process has become evermore sensitive and more vulnerable to yield loss, the incurred costs associated with such losses is continuing to increase in the form of higher reticle costs, longer cycle times for learning, increased costs associated with the lithography tools, and most importantly lost revenue due to bringing a product to market late. This has resulted in an increased need for virtual manufacturing tools that are capable of accurately simulating the lithography process and detecting failures and weak points in the layout so they can be resolved before committing a layout to silicon and / or identified for inline monitoring during the wafer manufacturing process. This paper will attempt to outline a verification flow that is employed in a high volume manufacturing environment to identify, prevent, monitor and resolve critical lithography failures and yield inhibitors thereby minimizing how much we succumb to the aforementioned semiconductor manufacturing vulnerabilities.

Reverse engineering source polarization error

With the advent of the first immersion and hyper-NA exposure tools, source polarization quality will become a hot topic. At these oblique incident angles, unintentional source polarization could result in the intensity loss of diffraction orders possibly inducing resolution or process window loss. Measuring source polarization error on a production lithographic exposure tool is very cumbersome, but it is possible to reverse engineer any source error similarly to what has been accomplished with intensity error. As noted in the intensity maps from the source illumination, it is not safe to assume an ideal or binary source map, so model fitness is improved by emulating the real error. Likewise, by varying the source polarization types (TE, TM, Linear X and Linear Y) and ratios to obtain improved model fitness, one could deduce the residual source polarization error. This paper will show the resolution and process window gain from utilizing source polarization in immersion lithography. It will include a technique demonstrating how to extract source polarization error from empirical data using the Calibre model and will document the modeling inaccuracy from this error.