Chi-Yuan Lo

The Second Generation MOTIS Mixed-Mode Simulator

This paper describes the second generation MOTIS mixed-mode simulator. In particular, It extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with local time-step control for timing simulation, and a switch level approach for unit delay simulation. It provides logic and timing verification for general MOS circuits in a mixed-mode environment. The new simulator is being used for production chips, and it is more accurate, flexible, and efficient than the existing MOTIS mixed-mode simulator.

GENAC: An Automatic Cell Synthesis Tool

We present a solution to the layout problem of cell synthesis, which achieves multiple optimization objectives. In particular, we propose a new hierarchical method for fast and optimal placement of the transistors in a cell. The method minimizes the number of diffusion breaks, and allows a further pursuit of a secondary optimization objective, such as routing channel density. For cells with non-uniform transistor widths, the transistors are folded in such a way as to optimize a cost function which is a good approximation to the area of the final (compacted) layout of the cell. We also analyze the characteristic nature of routing in cell generation problem, and design an algorithm for doing routing over the transistors; such routing reduces the routing channel density in the central region of the cell. The routing in the central region is completed by a new channel router at, or near, the channel density. The algorithms are implemented in a system call GENAC. The input to GENAC is a transistor net list, describing the connectivity as well as the size and type of each transistor. The output is a synthesized layout of the cell in symbolic language.

A Fault Simulator for MOS LSI Circuits

This paper describes a fault simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. The simulator provides the capability of modeling and simulating both the classical input/output stuck-at faults and the non-classical transistor stuck-on and stuck-open faults.

Algorithms for an Advanced Fault Simulation System in MOTIS

In this paper, we will present algorithms developed for an advanced fault simulation system in the MOTIS simulation environment. In particular, the algorithm to perform fault modeling and collapsing is first reviewed. Efficient algorithms to perform fault simulation are discussed in terms of fault list manipulation and primitive evaluation. The simulator realizes a speed gain factor of 787 to 2088 over serial fault simulation. Special emphasis is on an innovative fast unit delay fault simulation algorithm that achieves an additional 33-39-percent improvement in speed and 20-28-percent improvement in memory usage.

Time-efficient VLSI artwork analysis algorithms in GOALIE2

New algorithms used in the GOALIE2 circuit extraction system, based on representing VLSI layout geometries as trapezoids, are presented in this paper. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. In particular, the scanline algorithm virtually eliminates all redundant computation present in similar systems. These algorithms enable us to perform VLSI layout analysis in nearly linear time.

An O(n/sup 1.5/ log n) 1-d compaction algorithm

In this paper, we bound the complexity of the major algorithms of 1-d compaction in graph solution and module assembly to be &Ogr;(<italic>n</italic><supscrpt>15</supscrpt>log<italic>n</italic>). An 1-d hierarchical module assembly method is shown to be free from the x-y interlock problem and achieves significant improvement in space and time requirements by exploiting hierarchy.

A Data Structure for MOS Circuits

This paper describes a data structure to represent the driver-load configurations in MOS circuits, which is used universally in the MOTIS simulation environment. In particular, the data structure is used in mixed-mode evaluation including timing, and multiple/unit delay. Other applications include automatic delay calculation, transistor fault modeling, fault collapsing, and fault simulation.

On minimal closure constraint generation for symbolic cell assembly

Consider the problem of finding all pair longest paths for a subset of vertices P E V in a weighted directed graph G = (V, E). A closure constraint wij exists if the Ion est path length between vi E P and vi E P is finite. Denote f P I = p . we present an algorithm that generates significantly less closure constraints than O@’). For symbolic layout cell abstraction, the size of the reduced set has been found to be I c-p. where c S 10. This has significant implications for improving the efficiency of various symbolic cell assembly methods.

An Efficient Two-Dimensional Layout Compaction Algorithm

A new heuristic two-dimensional symbolic layout-compaction approach is developed. After conventional one-dimensional compaction steps, all the components on the critical paths that define the height or width of the given layout are found and rearranged to reduce the layout size. During this process, constraints in both x and y directions are considered and pitch-matching of ports for hierarchical compaction can be achieved to reduce the amount of the design data. This approach generated the smallest area for several examples we have tried when compared with other published results. The expected run time can be bounded by O(T/sub 1/, where T/sub 1/ is the run time of a typical one-dimensional compactor.

An O(n log m) Algorithm for VLSI Design Rule Checking

This paper describes a new variant of the segment tree approach for VLSI design rule checking. The best known algorithms to date for flat VLSI design rule checking require O(n log n) expected time and PI expected space, where n is the total number of edges on a mask layer of the chip. We present a new algorithm that can run in O(n log m) expected time, where m is the maximum feature size on a particular mask layer. Since the maximum feature size must be bounded by the height of a chip, i.e. m ≤ O(√n), the new algorithm is adaptively more efficient than O(n log n). For layers such as diffusion or contact windows where the maximum feature size is independent of chip size, i.e. m = O(1), the new algorithm runs in O(n) expected time, a definite improvement. The improved time efficiency is achieved without sacrificing (√n) expected space complexity.