Chia-Hsiang Yang

A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wireless power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30- μA stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18- μm CMOS and occupies 13.47 mm2. Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy (> 92%) within 0.8 s.

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example

This paper presents a design methodology for power and area minimization of flexible FFT processors. The methodology is based on the power-area tradeoff space obtained by adjusting algorithm, architecture, and circuit variables. Radix factorization is the main technique for achieving high energy efficiency with flexibility, followed by architecture parallelism and delay line circuits. The flexibility is provided by reconfigurable processing units that support radix-2/4/8/16 factorizations. As a proof of concept, a 128- to 2048-point FFT processor for 3GPP-LTE standard has been implemented in a 65-nm CMOS process. The processor designed for minimum power-area product is integrated in 1.25 × 1.1 mm2 and dissipates 4.05 mW at 0.45 V for the 20 MHz LTE bandwidth. The energy dissipation ranging from 2.5 to 103.7 nJ/FFT for 128 to 2048 points makes it the lowest energy flexible FFT.

A Flexible DSP Architecture for MIMO Sphere Decoding

This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequency subcarriers for orthogonal frequency-division multiplexing (OFDM) based systems. A 20 times area reduction is achieved, even without interleaving of subcarriers compared to the direct-mapped architecture. The sphere decoder supports multiple configurations: antenna arrays from 2 times 2 to 16 times 16, constellation sizes from binary phase-shift keying (BPSK) to 64-QAM (quadrature-amplitude modulation), and 16-128 subcarriers. The peak estimated data rate exceeds 1.5 Gbits/s of ideal throughput in a 16-MHz bandwidth. The core area is estimated at 0.31 mm2 in a standard 90-nm CMOS technology. The estimated power consumption is 33 mW in the 16 times 16 64-QAM mode at 256 MHz from a 1-V supply voltage.

A hierarchical approach for online temporal lobe seizure detection in long-term intracranial EEG recordings

OBJECTIVE Around 1% of the worlds population is affected by epilepsy, and nearly 25% of patients cannot be treated effectively by available therapies. The presence of closed-loop seizure-triggered stimulation provides a promising solution for these patients. Realization of fast, accurate, and energy-efficient seizure detection is the key to such implants. In this study, we propose a two-stage on-line seizure detection algorithm with low-energy consumption for temporal lobe epilepsy (TLE). APPROACH Multi-channel signals are processed through independent component analysis and the most representative independent component (IC) is automatically selected to eliminate artifacts. Seizure-like intracranial electroencephalogram (iEEG) segments are fast detected in the first stage of the proposed method and these seizures are confirmed in the second stage. The conditional activation of the second-stage signal processing reduces the computational effort, and hence energy, since most of the non-seizure events are filtered out in the first stage. MAIN RESULTS Long-term iEEG recordings of 11 patients who suffered from TLE were analyzed via leave-one-out cross validation. The proposed method has a detection accuracy of 95.24%, a false alarm rate of 0.09/h, and an average detection delay time of 9.2 s. For the six patients with mesial TLE, a detection accuracy of 100.0%, a false alarm rate of 0.06/h, and an average detection delay time of 4.8 s can be achieved. The hierarchical approach provides a 90% energy reduction, yielding effective and energy-efficient implementation for real-time epileptic seizure detection. SIGNIFICANCE An on-line seizure detection method that can be applied to monitor continuous iEEG signals of patients who suffered from TLE was developed. An IC selection strategy to automatically determine the most seizure-related IC for seizure detection was also proposed. The system has advantages of (1) high detection accuracy, (2) low false alarm, (3) short detection latency, and (4) energy-efficient design for hardware implementation.

DSP architecture optimization in Matlab/Simulink environment

An automated architecture optimization for DSP algorithms within graphical Matlab/Simulink environment is proposed. The optimization uses Integer Linear Programming for scheduling and retiming of hardware blocks. The high-level block-diagram based Simulink model maps to FPGA or ASIC. Users can control the tuning range of architecture parameters and select solutions from energy-area-performance tradeoff space. The hierarchical method produces optimal architectures with energy efficiency of 5GOPS/mW in a 90 nm CMOS technology.

A 1.2V 6.7mW impulse-radio UWB baseband transceiver

A 2.7mm/sup 2/ CMOS baseband transceiver IC for impulse-radio UWB communication systems is implemented in a 0.18 /spl mu/m CMOS process. This chip provides up to 62.5Mbit/s data transmission for short-range wireless communications while drawing 6.7mW from a 1.2V power supply.

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz , achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.

A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications

The sphere decoding algorithm finds applications in multi-input multi-output (MIMO) decoding, because it achieves near maximum likelihood (ML) detection performance with significantly reduced computational complexity. Previous work has focused on implementations based on K-best or depth-first search, limiting the BER performance or the search speed. This paper presents a scalable multi-core sphere decoder architecture that can combine the advantages of the K-best and depth-first search methods. The proposed architecture demonstrated a 3-5 dB improvement in the BER performance for 16times16 systems using 16 processing elements (PEs) compared to the architecture with one PE. An improved search speed of the multi-core architecture also enables a 10times energy efficiency improvement over the single core architecture for the same data rate.

A wideband analog correlator system for AMiBA

A wideband correlator system with a bandwidth of 16 GHz or more is required for Array for Microwave Background Anisotropy (AMiBA) to achieve the sensitivity of 10μK in one hour of observation. Double-balanced diode mixers were used as multipliers in 4-lag correlator modules. Several wideband modules were developed for IF signal distribution between receivers and correlators. Correlator outputs were amplified, and digitized by voltage-to-frequency converters. Data acquisition circuits were designed using field programmable gate arrays (FPGA). Subsequent data transfer and control software were based on the configuration for Australia Telescope Compact Array. Transform matrix method will be adopted during calibration to take into account the phase and amplitude variations of analog devices across the passband.

Erythropoietins from teleosts

Abstract.The epo genes of many teleosts, including zebrafish, have been cloned following the first identification of nonmammalian EPO from fugu in 2004. The zebrafish (Danio rerio) animal model is well suited for both developmental and genetic analyses for studying vertebrate erythropoiesis. The purpose of this review is to provide an update of recent progress in research on teleost EPO with a focus on its structure, expression and secretion. The EPO receptor and the downstream JAK/STAT signaling pathway are also discussed.